FoRTReSS Tool Box is now available !

FoRTReSS is an academic research project. It is a tool suite providing the user a way to explore the partial reconfiguration design space and ultimately proposing a set of reconfigurable regions and processors that will ensure a certain quality of service for a given application. FoRTReSS can be integrated into existing PR flows. It is placed between the synthesis phase, where all reconfigurable modules are synthesized into netlists, and the implementation phase, where the floorplan is created. FoRTReSS takes as an input netlists, synthesis reports and the targeted device from the first step. It also needs some more information about the application, in the form of a Control Data Flow Graph (CDFG) and additional timing information (e.g. execution times and deadline). To validate a solution, FoRTReSS relies on a SystemC simulator, called RecoSim. The flow is modular and each step can be customized in order to facilitate design space exploration by the designer.

What is Dynamic & Partial Reconfiguration ?

Over the last few decades, reconfigurable computing has emerged, making use of Field Programmable Gate Arrays' (FPGA) parallel processing power. When a complete system is built on a single FPGA, possibly including processors, memory controllers, or hardware accelerators, we talk about System on Programmable Chip (SoPC). However, every part of the chip may not be active at the same time (for instance, activating a hardware accelerator depending on the application running on the processor), resulting in an area and energy consumption inefficiency.


Dynamic and partial reconfiguration has been developed to deal with this situation. Partial Reconfiguration (PR) is an FPGA feature introduced in the late 1990s that allows altering the behaviour of some pre-defined Reconfigurable Regions (RR) while the remaining logic is still running. Therefore, it is possible to change the functionality of a system, reduce the global area needed by a design and either choose a smaller FPGA or embed more features inside the targeted FPGA.

FoRTReSS Integration