Programme et Résumés


Table des matières

  1. 1 Session Applications Biomédicales, IoT et Technologies Émergentes
    1. 1.1 Ultrasonic imaging perspectives - from piezoelectric transducers to CMUTs and polyCMUTs, Edmond Cretu (UBC Vancouver, CA)
    2. 1.2 Smart biosensors for a HEALTHY YOU – towards an Integrative Technological Platform for Personalized, Preventive and Participatory (P3) Healthcare, Adrian Ionescu (EPFL, CH)
    3. 1.3 Smart biosensors for a HEALTHY YOU – towards an Integrative Technological Platform for Personalized, Preventive and Participatory (P3) Healthcare, Adrian Ionescu (EPFL, CH)
    4. 1.4 From Design-Technology Co-Opimization to System-Technology Co-Optimization, Julien Ryckaert (IMEC, BE) 
    5. 1.5 Circuits intégrés en 3D: technologies, problèmes de conception associés, les solutions et les avantages système, Dragomir Milojevic (ULB, BE
    6. 1.6 New logic paradigms based on vertical NanoWire FET: The coming LEGO technology, Cristell Maneux (IMS Bordeaux, FR)
    7. 1.7 Panel: e-Health, Adrian Ionescu / Laurent Francis
  2. 2 Session Nouveaux Paradigmes de Calcul et Architectures Systèmes
    1. 2.1 Artificial Intelligence: basis and impact on hardware development., Carlo Reita  (CEA-Leti, FR)
    2. 2.2 Exploiting Approximate Computing to Increase System Lifetime, Alberto Bosio (EC Lyon, FR)
    3. 2.3 In-Memory and Error-Immune Differential RRAM Implementation of Binarized Deep Neural Networks, Marc Bocquet (AMU Marseille, FR)
    4. 2.4 AdequateDL: Approximating Deep Learning Accelerators, Olivier Sentieys (INRIA, FR)
    5. 2.5 Autonomic Management of Reconfigurations in DPR FPGA and potentials towards integration in Data-Centers, Eric Rutten (INRIA, FR)
    6. 2.6 Energy-Efficient NVM Memory Mapping based on delta-WCET Analysis, Abdoulaye Gamatié (LIRMM, FR)
    7. 2.7 Computation-in-Memory: What is it about and how big is its potential?, Said Hamdioui (TU Delft, NL)
    8. 2.8 Panel, David Bol
  3. 3 Session Systèmes HW / SW et EDA
    1. 3.1 Indirect Time of Flight technology for 3D sensing, Morin Dehan  (Sony Depthsensing Solutions, BE)
    2. 3.2 Device-technology co-optimization for RF applications, Bertrand Parvais (IMEC, BE)
    3. 3.3 Méthodes agiles dans la conception matérielle, Olivier Tesson (NXP, FR)
    4. 3.4 Estimating power consumption and battery life at early design stage using system-level simulation, Wilfried Dron (Wisebat, FR)
    5. 3.5 Can we supply IoT smart sensors wirelessly through simultaneous wireless and power transfer (SWIPT) ?, David Bol (UCL, BE)
    6. 3.6 SHNoC: Reliable Multi-Technologies Network-on-Chip, Cédric Killian  (IRISA, FR)
    7. 3.7 A study of shared memory influence on multi-core real-time systems, Youcef Bouchebaba (ONERA, FR)
    8. 3.8 Runtime assertion-based verification for correctness and reliability analysis, Laurence Pierre (IMAG, FR)
    9. 3.9 Panel : systèmes de demain, Bertrand Granado
  4. 4 Session Cryptographie et Sécurité
    1. 4.1 Towards Physically-Secure Implementations (& the Need of Theory, Practice and Open Designs), François-Xavier Standaert (UCL, BE)
    2. 4.2 Protocole léger de sécurisation de systèmes IoT à base de radio de réveil contre les attaques par déni de sommeil, Simone Bacles-Min (CEA-Leti, FR)
    3. 4.3 Designing Systems with Detection and Recongufiration Capabilities: A Formal Approach, Saddek Bensalem (IMAG, FR)
    4. 4.4 On the applicability of binary classification to detect memory access attacks in IoT, Anca Molnos (CEA, FR)
  5. 5 Session Circuits et Composants
    1. 5.1 Wake-up radios : principe, état de l'art, évolution et application clés vers les wake-up sensors et wake-up imagers, Dominique Morche (CEA, FR)
    2. 5.2 Integrated circuit design towards a smart world, Georges Gielen (KUL, BE)
    3. 5.3 Conception d'une unité de pré-traitement à faible énergie pour les "smart sensors", Benoit Larras (ISEN Lille, FR)
    4. 5.4 Wireless Network-On-Chip for Long-Range and Broadcast Communications, Jean-Philippe Diguet (Lab-STICC, FR)
    5. 5.5 Capteurs CMOS physiques & physiologiques flexibles et basse consommation, Denis Flandre (UCL, FR)
    6. 5.6 OpticALL2: on-chip OPTIcal interconnect for ALL to ALL communications, Sébastien Le Beux (ECL, FR)
    7. 5.7 Intégration monolithique de SPAD dans une technologie CMOS FDSOI, Francis Calmon (INSA Lyon, FR)
    8. 5.8 Modeling of ultra-low-voltage MOS circuits, Carlos Galup Montoro (UFSC, Brésil)
    9. 5.9 No digital society without sustainable information technology, Jean-Pierre Raskin (UCL, BE) / Thomas Ernst (CEA-Leti, FR)
    10. 5.10 Panel: Electronique durable, Jean-Pierre Raskin / Thomas Ernst

Session Applications Biomédicales, IoT et Technologies Émergentes

Ultrasonic imaging perspectives - from piezoelectric transducers to CMUTs and polyCMUTs, Edmond Cretu (UBC Vancouver, CA)

The presentation will present some state-of-the-art and trends aspects pertaining to the ultrasound imaging technology, mainly related to transducer advances and biomedical imaging applications. The theory of capacitivie micromachined ultrasonic arrays, their fabrication technology and their modeling will be presented, complemented by potential future applications.

Smart biosensors for a HEALTHY YOU – towards an Integrative Technological Platform for Personalized, Preventive and Participatory (P3) HealthcareAdrian Ionescu (EPFL, CH)

In this presentation we will report the general Integrative Technological Platform for Personalized, Preventive and Participatory (P3) Healthcare, as proposed by the Health EU initiative, combining Edge Internet-of-Things sensors, Artificial Intelligence and Big Data Analytics.

We will discuss the importance of energy efficient zettabyte ICT technologies for making more sustainable one of the key fields of modern society, the healthcare. The continuing health of our societies is increasingly threatened by the enormous cost of providing appropriate healthcare in the rapidly ageing societies. Changing of strategies based on the exploitation of advanced ICT technologies has been implemented in most areas of our existence, increasing their efficiency and reducing costs. However, the healthcare is taking very little of the enormous progress achieved today in emerging ICT technologies.

The concept of a Human Avatar is a point of convergence for the latest biomedical research and disruptive future digital platforms: the Internet of Things, Digital Twins and Artificial Intelligence, combining the three most vibrant fields of technology of our time. In this context, Health EU’s Human Avatars are planned in the context of a global European Integrative Human Avatar Platform, including interdisciplinary innovation boosters, infrastructure and deployment related to the requirement of an affordable Universal Healthcare System for every citizen.

Another particular point of focus of the presentation will be on the recent progress made in wearable technologies and smart biosensors, illustrated with examples from the Flag Era Convergence project.

Smart biosensors for a HEALTHY YOU – towards an Integrative Technological Platform for Personalized, Preventive and Participatory (P3) HealthcareAdrian Ionescu (EPFL, CH)

tbd

From Design-Technology Co-Opimization to System-Technology Co-OptimizationJulien Ryckaert (IMEC, BE) 

By 2020 Moore's Law will see an unprecedented pressure. It is already a fact that since the 20nm node, the happy scaling era where dimensional scaling was the fuel to generate cheaper, faster and more power efficient technology nodes ran out of steam. Today, technologists use all possible "technology enablers" or "boosters" to keep the prophecy alive. These techniques trade design requirements with specific technology capabilities in a so-called design-technology co-optimization (DTCO) framework. Circuit designers and technologists build together the next generation nodes by adapting to their respective constraints. It is anticipated that soon this approach will have to extend to the system level leading to system-technology co-optimization (STCO). In this evolution, recognizing the heterogeneity of integrated circuits and the specificities of each applications, I hybrid technology offering can provide the best adapted solutions to build faster, cheaper and power efficient systems. In this way, techniques such co-integration of advanced devices in CMOS platforms, 3DIC or sequential 3D become essential ingredients to realize a cost-effective hybridization. However, it is clear that the efficiency of these technology offerings will highly depend on the strength of the interactions between all the different stakeholders in the VLSI community.

Circuits intégrés en 3D: technologies, problèmes de conception associés, les solutions et les avantages système, Dragomir Milojevic (ULB, BE

La réduction de la taille des transistors et une plus grande densité fonctionnelle des circuits intégrés sont rendus de plus en plus difficiles avec les technologies CMOS traditionnels en dessus de 10nm. L'intégration des circuits en 3D, où plusieurs couches de transistors (portes logiques) sont implémentés au sein d'un même circuit intégré, est proposé comme complément du /scaling/ traditionnel. Dans cette exposé nous proposons dans un premier temps un panoramas des différentes technologies d'intégration 3D. Ensuite, nous exposerons des problèmes de conception de tels circuits liés à la synthèse, le partitionnement, le placement & le routage. Enfin, des exemples d'implémentations des circuits concrets seront présentés pour illustrer les potentiels avantages de cette technologie en termes des gains en performance, en superficie de circuit et de la puissance dissipée.

New logic paradigms based on vertical NanoWire FET: The coming LEGO technologyCristell Maneux (IMS Bordeaux, FR)

This presentation introduces the coming LEGO technology (Logic Elements using Gate Overstaking) from different complementary points of view in the fields of (i) vertical n- and p- NanoWire Field Effect based 3D-transistors fabrication, (ii) compact modelling of emerging devices, (iii) design of innovative architectures based on emerging technologies, (iv) design of test chips for 3D system integration. Such a gathering intents to achieve innovative logic circuit demonstrators based on arrays of vertical nanowire-based transistors. This technology could be considered to be the prime candidate for demonstrating new concepts at transistor and circuit level which bring the potential of highly improved performance for generic applications. Indeed, today, the acceptability of new logic paradigms based on emerging technologies is hindered by the lack of proof that such approaches actually work. Therefore, there is a need to:

- Develop ground-breaking stacked vertical n- and p- NanoWire Field Effect Transistor technology,
- Develop compact models and full design kit (PDK) to support the circuit design process,
- Design, build and test 3D logic blocks based on stacked regular fabrics of vertical NWFETs and prove enhanced logic functionality and logic circuit operation, 
- Assess the technology roadmap improvements and associated logic architecture performance metrics.

The coming LEGO technology is expected to deliver proof for monolithic 3D stacks of vertical NWFET to address challenges of compactness, heat dissipation, reduced interconnect length.

Panel: e-HealthAdrian Ionescu / Laurent Francis

Session Nouveaux Paradigmes de Calcul et Architectures Systèmes

Artificial Intelligence: basis and impact on hardware development.Carlo Reita  (CEA-Leti, FR)

Research activities in the field of brain-inspired computing have gained a large momentum in recent years. The main reason is the attempt to go beyond the limitation of the conventional Von Neumann architecture that is increasingly affected by the limitation of the bandwidth and latency of the memory-logic communication. In neuromorphic architectures, the memory is distributed and can be co-localised with the logic, in particular it is what the new resistive memories technologies could provide. While most of the attention is being directed to implementation of Deep Learning algorithms in large computing system, the impact on device and circuit technology has been mixed. On one hand, advanced standard CMOS technology has been used to develop GPU and specific circuit accelerators without making use of any “bio-inspired” hardware. On the other hand, emerging resistive memory devices (RRAMs) are considered good candidates to emulate a biologically plausible synaptic behavior at nanometer scale, because of the fact that they offer the possibility to modulate their conductance by applying low biases, and can be easily integrated with CMOS-based neuron circuits in a back-end process during the making of the chip. This has opened the way for the realization of compact and energy-efficient computing architectures based on artificial neural networks (ANNs) – mainly using unsupervised learning rules such as the Spike Timing Dependent Plasticity - but that have been restricted mostly to the research community due to the insufficient maturity of the technology.

After an initial reminder of the basic principles, this paper will review some of the approaches for neuromorphic computing as an approach for the future of computing. and some possibility for beyond deep learning and brute force digital approaches will be discussed.

Exploiting Approximate Computing to Increase System LifetimeAlberto Bosio (EC Lyon, FR)

Approximate Computing (AxC) is today one of the hottest topics related to system design and optimization. Thanks to this computing paradigm, designers are able to reduce area, power consumption, and even production costs in the case the target application can accept a given degree of inaccuracy in the final computations. This talk discusses the impact of Approximate Computing on the system reliability. More in particular, it aims at showing that it is possible to use Approximate Computing to implement efficient fault tolerant architectures. The ultimate goal is to determine the trade-off between the degree of the approximation VS the reliability to finally increase the system lifetime.

In-Memory and Error-Immune Differential RRAM Implementation of Binarized Deep Neural NetworksMarc Bocquet (AMU Marseille, FR)

RRAM-based in-Memory Computing is an exciting road for implementing highly energy efficient neural networks. This vision is however challenged by RRAM variability, as the efficient implementation of in-memory computing does not allow error correction. In this work, we fabricated and tested a differential HfO2-based memory structure and its associated sense circuitry, which are ideal for in-memory computing. For the first time, we show that our approach achieves the same reliability benefits as error correction, but without any CMOS overhead. We show, also for the first time, that it can naturally implement Binarized Deep Neural Networks, a very recent development of Artificial Intelligence, with extreme energy efficiency, and that the system is fully satisfactory for image recognition applications. Finally, we evidence how the extra reliability provided by the differential memory allows programming the devices in low voltage conditions, where they feature high endurance of billions of cycles.

AdequateDL: Approximating Deep Learning Accelerators, Olivier Sentieys (INRIA, FR)

The design and implementation of convolutional neural networks for deep learning is currently receiving a lot of attention from both industrials and academics. However, the computational workload involved with CNNs is often out of reach for low power embedded devices and is still very costly when run on datacenters. By relaxing the need for fully precise operations, approximate computing substantially improves performance and energy efficiency. Deep learning is very relevant in this context, since playing with the accuracy to reach adequate computations will significantly enhance performance, while keeping quality of results in a user-constrained range. ​AdequateDL will explore how approximations can improve performance and energy efficiency of hardware accelerators in deep-learning applications. Outcomes include a framework for accuracy exploration and the demonstration of order-of-magnitude gains in performance and energy efficiency of the proposed adequate accelerators with regards to conventional CPU/GPU computing platforms.

FPGA-based architectures can offer support for high flexibility through dynamic partial reconfiguration (DPR) features. This enables the switch at runtime between different computations, or different implementations of the same computation, with different characteristics in resource usage (e.g., FPGA surface) and performance (e.g. QoS). In turn, this provides support for the system to dynamically adapt itself to uncertainties related to the environment, or to the data being processed. We consider self-adaptive embedded systems, such as UAVs, involving an offline provisioning of the several implementations of the embedded functionalities (e.g. video processing). We propose an autonomic management architecture for self-adaptive and self-reconfigurable FPGA-based embedded systems. The control architecture is responsible for decision and choice of configurations, and is structured in three layers: a mission manager, a reconfiguration manager and a scheduling manager. We will draw perspectives on the use of DRP FPGA in the context of Data-Centers, as a shared resource for acceleration.

Energy-Efficient NVM Memory Mapping based on delta-WCET AnalysisAbdoulaye Gamatié (LIRMM, FR)

This talk deals with the efficient usage of emerging non-volatile memories in embedded systems. Such memories have a negligible static power consumption compared to classical memories, e.g., SRAM or DRAM. However, they have expensive write operations, both in terms of latency and energy. In order to mitigate this detrimental feature, we leverage the notion of delta worst-case execution time based on program analysis. This enables to efficiently allocate data onto NVM memory banks with variable data retention times. The talk will lay down the intuition behind such an approach and will report potential gains in terms of memory dynamic energy.

TbdDaniel Chillet (INRIA, FR)

tbd

Computation-in-Memory: What is it about and how big is its potential?, Said Hamdioui (TU Delft, NL)

It is well recognized that today’s computer architectures (mainly von Neumann architectures) are facing serious challenges, likewise is the COMS technology.  This means that emerging applications being extremely demanding and have surpassed the capabilities of today’s computational architectures and technologies. Hence, in order for computing systems to continue delivering sustainable benefits for the foreseeable future society, alternative computing architectures have to be explored. The  emerging new device technologies could play a key role in this exploration. In-memory computing based on memrsitive devices is one of the most promising computational approaches being pursued,

This talk will first address the limitation of both CMOS scaling and today’s computing architectures. Then the concept of computation-in-memory will be discussed. Logic and arithmetic circuit designs enabling such architectures will be covered. The huge potential of such architecture in realizing order of magnitude improvement will be illustrated by comparing it with the state-of-the art architectures for different data-intensive applications.

Panel, David Bol

Session Systèmes HW / SW et EDA

Indirect Time of Flight technology for 3D sensingMorin Dehan  (Sony Depthsensing Solutions, BE)

Solid state 3D Time-of-Flight technology made its research entrance in the 90’s and is now slowly starting to be adopted in a number of applications. Mobile platforms such as ‘Google Tango’-enabled smartphones or VR/AR headset are today equipped with ToF technology for 3D sensing. In the industrial world, ToF technology is today mainly linked with robotics and safety/security vision systems, competing with established distance sensor solution based on structured light and stereo-vision. This talk aims to give a brief overview on 3d sensing technology, and on what it takes to develop a ToF system, from designing the imager to developing the sensing solution, including camera module and computer vision software.

Device-technology co-optimization for RF applicationsBertrand Parvais (IMEC, BE)

Les nouvelles générations de systèmes de communications mobiles (5G et suivantes) appellent à innover non seulement dans l’infrastructure globale du réseau, mais aussi dans les technologies destinées aux appareils mobiles. Dans cette présentation, les liens entre les spécifications des circuits RF et les besoins technologiques seront mis en évidence.  D'une part, afin d’aider les concepteurs de circuits à mieux comprendre les spécificités des nouvelles technologies; d'autre part, pour orienter les développements technologiques en fonction des besoins des prochaines générations de radio. Dans ce contexte, la modélisation des transistors et de leurs parasites est cruciale et les principales caractéristiques des transistors en technologies Silicium et III-V seront examinées.

Méthodes agiles dans la conception matérielleOlivier Tesson (NXP, FR)

tbd

Estimating power consumption and battery life at early design stage using system-level simulationWilfried Dron (Wisebat, FR)

When engineers are designing a new device they need to choose components. While state-of-the-art methods strongly recommend to use modelling and simulation before building a first prototype, most of the engineers prefer to start with real hardware (mainly because modeling and simulating is time intensive). However, with an ever-growing component offer, comparing components is more and more complicated. In this presentation we will see how we can easily and quickly model a system to estimate its characteristics like power consumption or battery life. We will also explore several case studies where our approach allow engineers to shorten the design time by 3 month while dramatically increasing their ability to explore different solutions.

Can we supply IoT smart sensors wirelessly through simultaneous wireless and power transfer (SWIPT) ?, David Bol (UCL, BE)

Battery replacement in wireless IoT applications has both an economical and an environmental burden. For ultra-low-power and ultra-low-cost IoT smart sensors, ambient energy harvesting can be used as an alternative to primary battery. However, the difficulty to predict the availability of ambient power sources makes the practical deployment difficult without resorting to mAh rechargeable batteries as energy storage, which impedes the cost, form factor and environmental footprint. Intentional wireless power transfer can be used as a reliable supply mechanism. In this talk, we will discuss the challenges fo supplying IoT smart sensors through wireless power transfer while simultaneously communicating in a SWIPT scheme. 

SHNoC: Reliable Multi-Technologies Network-on-ChipCédric Killian  (IRISA, FR)

Technology evolution has allowed for the integration of silicon photonics and wireless on-chip communications, creating Optical and Wireless NoCs (ONoCs and WNoCs, respectively) paradigms. Recent publications highlight specific advantages for each technology: WNoCs are efficient for broadcast, ONoCs have low latency and high integrated density (throughput/cm2), and ENoC are still efficient for average size of NoC. In this context, this project proposes to associate these three technologies. Each NoC technology possesses particular and complementary advantages allowing to efficiently route messages depending on their profile: short or long distance, uni- or multi-cast. Moreover, given the shrinking size of the transistors, on-chip architectures become more sensitive to faults. As the access of ONoC and WNoC are handled through shared interfaces, they become critic resources, and any fault can severely degrade the performance of the whole communication architecture. This project proposes the definition and management of a Scalable Hybrid NoC (SHNoC) associating electric, optic and wireless communication media to take advantage of each technology. Adaptive Quality of Service will be proposed to efficiently route the messages on the most efficient technology with respect to constraints. Moreover, we propose to integrate fault-tolerance mechanisms to ensure the overall performance of the SHNoC and combine them with adaptive QoS protocol that will take into account any degraded access point to adapt its decisions on run-time. 

A study of shared memory influence on multi-core real-time systemsYoucef Bouchebaba (ONERA, FR)

Real-time embedded systems are facing increasing complexity of both software and hardware implementations. This come from the need to integrate multiple functionalities within the same application, but also from the quest for performance of autonomous systems. Multi-core platforms with shared resources, real-time operating systems, and sophisticated applications combine for unintentional interferences which have an impact in the execution time of critical tasks being executed. This talk proposes a  methodology to determine different families of interferences occurring on such a platform. Their impact on execution time will be quantified and modeled. In doing that, we focus on interferences due to shared memories within the T4240 multi-core platform and the PikeOS hypervisor. A set of experiments have been conducted so as to produce interferences on a critical task, by using multiple non-critical cores and different memory requirements and cache uses.

Runtime assertion-based verification for correctness and reliability analysisLaurence Pierre (IMAG, FR)

Analyzing the correctness and the reliability of C or C++ embedded software is a crucial issue. Runtime ABV (assertion-based verification) can help alleviate this process. It aims to check whether the software application obeys properties, formalized as logico-temporal formulas (assertions). We summarize the principles of a tool that has been developed to perform such verifications, and we describe experiments for two embedded applications.

Panel : systèmes de demainBertrand Granado

Session Cryptographie et Sécurité

Towards Physically-Secure Implementations (& the Need of Theory, Practice and Open Designs)François-Xavier Standaert (UCL, BE)

In this talk, I will survey recent approaches/results to obtain physical security against side-channel attacks exploiting leakages, such as an implementation's power consumption. After a brief introduction and motivation, I'll describe how these attacks proceed (i.e., the so-called standard DPA setting) and why purely hardware-level (practical, heuristic) countermeasures alone cannot solve the problem. I will then discuss how the impact of hardware-level countermeasures can be amplified thanks an algorithmic-level countermeasure called masking, how this amplification can be formally analyzed, and the implementation challenges that physical defaults can imply for the secure implementation of masking. I will conclude by discussing the need of an open approach to physical security, and the interest of re-designing cryptographic algorithms and protocols for this purpose.

Protocole léger de sécurisation de systèmes IoT à base de radio de réveil contre les attaques par déni de sommeilSimone Bacles-Min (CEA-Leti, FR)

Le domaine de l'IoT remet à plat de nombreux prérequis, notamment au niveau de la sécurité des objets connectés autonomes en énergie. Les nouvelles architectures se veulent les plus économes en énergie possible. L'implémentation de la sécurité dans l'IoT doit donc elle aussi être guidée par l'énergie disponible, sans pour autant mener à des failles de sécurité. Une « radio de réveil », ou Wake-up radio, est un type de radio à très faible consommation permettant de réguler la sortie de veille d’objets connectés dans l’Internet des Objets. Ce type de radio est apparu récemment comme une excellente solution afin de minimiser la consommation énergétique dans l’IoT, et est actuellement considéré pour être intégré dans une future version du Wi-Fi. Or, à cause de leur simplicité, ces radios sont particulièrement vulnérables à des attaques par déni de sommeil visant à vider la batterie d’un objet connecté. Afin de pallier à cette menace, nous proposons une méthode efficace et légère pour contrer ces attaques.

Designing Systems with Detection and Recongufiration Capabilities: A Formal ApproachSaddek Bensalem (IMAG, FR)

The design of functionally correct autonomous systems which operate in an unknown environment and that satisfy reliability, availability, maintainability, and safety (RAMS) requirements is a challenge. In this talk I will focus on the detection and reconfiguration features these systems must provide. Indeed, evolving in an  unknown environment can invalidate the assumptions made during the design phase. In particular, dierent hardware components might fail and provide erroneous inputs to the system, which will pass in a degraded mode where the expected RAMS do not hold anymore. Such faults need to be detected as early as possible and reconfiguration strategies must be applied to bring the system back into a nominal mode where the RAMS are satisfied. I will present an automated design process based on formal methods to develop Fault Detection, Isolation and Recovery (FDIR) components targeting partially observable timed systems.I will describe how to automatically synthesize runtime monitors, design reconguration strategies, and obtain full-edged FDIR components. I will illustrate the approach on a case study inspired from autonomous robotics applications.

On the applicability of binary classification to detect memory access attacks in IoTAnca Molnos (CEA, FR)

Many IoT end-nodes typically embed few compute resources which limits the implementation of security measures. IoT node's memory is a coveted target for attackers. Accessing the memory allows an attacker not only to access confidential data but also to have a complete control over the node.

In this talk, we discuss the utilisation of binary classification, i.e., Support Vector Machines, Random Forest, Decision Tree, Naive Bayes, Linear Discriminant Analysis, Quadratic Discriminant Analysis, and K Nearest Neighbour, to design lightweight memory access detectors. We compare the detection performance and complexity of these methods on a thermostat use-case. Experimental results indicate that even when trained on one simple attack, nonlinear classifiers (e.g., SVM and Naive Bayes) can detect different attacks in their earliest stages reducing by that the amount of leaked memory to few bytes.

Session Circuits et Composants

Wake-up radios : principe, état de l'art, évolution et application clés vers les wake-up sensors et wake-up imagersDominique Morche (CEA, FR)

Since the emergence of the basic principle of communicating objects, the power consumption of wireless communication has kept on decreasing. In the early days, the progress was mainly due to the silicon technology evolution. However, the influence of the technology is now limited and new approaches are needed. Recently, the concept of wake-up radio has known a renewed interest. High performance have been reached without the need for high Q external filter, as it was previously necessary. In this presentation, we will first review the different motivations for the wake-up radio, from the application up to the implementation. The state of the art of the existing devices will then be presented. Afterwards, we will emphasize that this IP should not only be considered as an additional radio components but rather as an additional system. This will be demonstrating by showing the impact of the protocol. Lastly, it will be shown that this approach is extended today to completely new applications such as imager, audio transducers or accelerometer. The presentation will conclude by opening the discussion onto the remaining challenges which need to be addressed to extend the application areas of such techniques.

Integrated circuit design towards a smart worldGeorges Gielen (KUL, BE)

The relentless progress of nanoelectronics and semiconductor technology fuels the technological revolution towards a smart world that immersively impacts our daily life, work and play. The Internet of Things, proactive healtcare monitoring, wellbeing comforting and home-care robots, cloud-based services, autonomous driving, industry 4.0, precision farming, etc. are but a few examples. Sensors and sensor interfaces with intelligence in the edge play a key role in all of these. This keynote will focus on core challenges in the design of future electronic circuits for these applications, where cost, power and reliability are the main issues, besides the raw performance. This will be illustrated with several practical design examples. 

Conception d'une unité de pré-traitement à faible énergie pour les "smart sensors"Benoit Larras (ISEN Lille, FR)

Dans le cadre de l'émergence de « l'Internet des Objets » et de l'intelligence ambiante, des quantités importantes de données sont amenées à transiter entre des capteurs embarqués et des unités centrales faisant l’agrégation et le traitement des données provenant de ces capteurs. Ces derniers envoient leurs informations en continu sans fil ou peuvent embarquer des unités de calcul génériques pour traiter les données à la volée au niveau du capteur. Du point de vue des capteurs, ces manières de procéder sont très coûteuses en termes de consommation énergétique et donc d'autonomie, car elles mettent à contribution en permanence les systèmes les plus gourmands en énergie. Le projet ANR JCJC LEOPAR s'inscrit donc dans le cadre du « Near-sensor computing » et vise à pré-traiter de manière efficace en énergie les signaux des capteurs, de manière à réduire les quantités de données à traiter ou à transmettre, et ainsi limiter le temps d'activation des systèmes consommant le plus d'énergie. Pour cela, l’objectif technique est de concevoir et fabriquer un circuit intégrant les fonctions d’extraction de caractéristiques et de classification, en utilisant des technologies en rupture avec l’état de l’art.

Wireless Network-On-Chip for Long-Range and Broadcast Communications, Jean-Philippe Diguet (Lab-STICC, FR)

Manycore systems require fast communication infrastructures to fulfill the inter-core communication requirements. Conventional wired Network On Chip has been introduced to provide bandwidth and flexibility but are facing scalability issues since the latency is increasing with the number of routers so number of hops. New interconnects technologies are emerging to address the long range multi-hop communication bottleneck such as three-dimensional (3D), photonics, and RF/wireless NoCs (WiNOCs). The photonic NoC achieves a higher bandwidth than WiNoC, but a high bandwidth is not necessarily the first constraint. Force instance parallel computing requires broadcast operations for synchronization based on short messages. Photon+IC NoC does not immediately provide broadcast capability which is naturally available with RF interconnects.Beyond broadcast capabilities, WiNoCs provide an end-to-end single-hop communication and so can be an efficient solution for improving the performance of parallel applications significantly. However if WiNoC is a promising solution it also raises multiple challenges. First the modelling of the radio channel is key issue to implement efficient and robust communications. Secondly the power consumption is a critical question, it is not realistic to plug a wireless interface to each core so efficient sizing and power management are required. Finally the usual token-passing protocol introduces a waiting time that can degrade the single-hop advantage of Wireless links. In this talk we will first introduce the WiNoC challenges and emerging solutions, we will present results for broadcast-based implementation of barrier-synchronisation, finally we will draw perspectives and current research topics.

Capteurs CMOS physiques & physiologiques flexibles et basse consommation, Denis Flandre (UCL, FR)

OpticALL2: on-chip OPTIcal interconnect for ALL to ALL communications, Sébastien Le Beux (ECL, FR)


Intégration monolithique de SPAD dans une technologie CMOS FDSOIFrancis Calmon (INSA Lyon, FR)

Single-Photon Avalanche Diodes (SPAD) have been widely studied and successfully implemented for the detection of weak optical signals in the visible and near-infrared spectrum range (NIR). They are able of capturing individual photons with typically sub-nanosecond timing resolution, which make them suitable for a wide area of application such as low light detection, time of flight measurements and more recently in secured or quantum communications.

The use of CMOS technologies allows low-cost, compact and reliable implementation of SPADs. Thus, CMOS SPAD-based sensors enter rapidly the consumer market. However, for more demanding applications such as image sensors (for 3D and/or time-resolved imaging), several technological challenges still need to be tackled. The current research efforts are mainly focusing on the increase of the fill factor and the photon detection efficiency for NIR photons. One way to keep the CMOS compatibility is to implement SPAD-based sensors with 3D-stacking of two tiers; one hosting the SPADs (with backside illumination), the other one hosting the associated electronics. Such a 3D-integration remains delicate and quite expensive since two dies need to be designed and fabricated, and then 3D assembled (at wafer level).

We introduce an original CMOS SPAD architecture implemented in CMOS FDSOI (Fully Depleted Silicon-on-Insulator) technology. The key idea is to use some specific features of advanced FDSOI technology to develop a novel 3D monolithically integration of SPAD pixel with back-side illumination. The expected benefits of such an integration are a much higher fill factor with state of-the-art performances, a cost effective and reliable solution for 3D SPAD and associated electronics implementation. After the SPAD architecture presentation, we present the promising preliminary results and future developments.

Modeling of ultra-low-voltage MOS circuitsCarlos Galup Montoro (UFSC, Brésil)

Ultra-low-voltage (ULV) circuits have gained considerable attention in recent years because of the emergence of small batteries and self-powered applications. Essential to the design of ULV circuits is an understanding of the transistor model and the meaning of its main parameters. We will review ultra-low-power circuits that allow the automatic extraction of the specific current IS and the threshold voltage VT of MOS transistors, which are fundamental parameters for circuit design and testing, as well as for technology characterization. 

No digital society without sustainable information technologyJean-Pierre Raskin (UCL, BE) / Thomas Ernst (CEA-Leti, FR)

The 21st century is the age of mobile communications and the conscious use of natural resources. Communication contributes to reduce distance between people. Smart objects communicate to each other to deploy an interactive environment (Internet of Things, IoT). People talk about the digital society. Everything seems to be fast, clean, reconfigurable, etc. but behind our screens there is an industry which requires, more than ever, space, energy and matter. Since tens of billions electronics objects are being disseminated all over the word in homes, buildings, cars, roads, etc., there is an urgent need to revisit the economic, technological, and societal models to develop a sustainable electronic industry that will care about its impact right from the design of these objects. Some key elements considered today in the emerging devices for IoT are rare or classified critical raw materials, they must be substituted or saved by orders of decade. In order to come up with efficient and sustainable solutions, scientists and engineers must embrace the complexity of the problems and adopt a systemic approach which favors an interdependent vision of the components of a problem.

No clear methodology exists today to design, manufacture and deploy the IoT in a “sustainable way” that preserves enough resources to avoid political, economic, and environmental tensions in the next twenty years. European microelectronics industry depends on rare-earth materials and noble metals, so called blood metals in Africa. European technology supplies are very fragile, and economy, strategic independence, ethical and environmental considerations are converging into a common requirement: design differently our technologies at the early stage of the research process.

Only a few initiatives have been launched in Europe and around the world to address the sustainable use of critical raw materials and none for developing sustainable wireless electronics devices which are going to be massively deployed within the digital society.

At the beginning of 2017, the European Nanoelectronics consortium on sustainability named ENCOS was established. The members of the consortium are today the Institut National Polytechnique de Grenoble (France), Cambridge University (UK), Ecole Polytechnique Fédérale de Lausanne (EPFL, Switzerland), Université catholique de Louvain (Belgium), Atomic Energy Research Centre (CEA, France), Fraunhofer-Institut für Zuverlässigkeit und Mikrointegration (Germany), and PuzzlePhone (Finland).

The consortium aims to develop methodologies applied to advanced research integrating the economic analysis, the geopolitics issues, the acceptability and the durability of new technological solutions.

Panel: Electronique durableJean-Pierre Raskin / Thomas Ernst

Ċ
Sébastien Le Beux,
31 janv. 2019 à 05:14
Ċ
Sébastien Le Beux,
25 janv. 2019 à 07:33
Comments