Elvis Pui-In Mak

High-/Mixed-Voltage Analog and RF Circuit Techniques for Nanoscale CMOS

Pui-In Mak (Elvis)

State-Key Laboratory of Analog and Mixed-Signal VLSI

University of Macau, Avenida Padre Tomas Pereira, Taipa, Macao SAR, China

IC designers may have already experienced the shortcomings of low supply voltage (V_DD) in ultra-scaled CMOS technologies. High-V_DD and mixed-V_DD techniques are emerged as a potential solution to deal with the problems induced by low-voltage constraints. By exploiting the well-established features of nanoscale processes such as: MOSFETs with multiple oxide thicknesses and V_DD driving capability, the performances of analog and RF circuits can be cost-efficiently improved. For instance, a hybrid use of core and I/O V_DD’s, thin-oxide and thick-oxide MOSFETs directly open up much freedom in topology selection, while fully benefiting the speed and area improvements of advanced processes. The key concern is on the circuit reliability which, however, can be ensured via proper biasing and use of startup/protection circuitry; both induce neglectable cost.

This page aims to provide an overview of the basic principles, system design considerations and examples relevant to high-V_DD and mixed-V_DD analog and RF circuits design. A wide variety of topologies from the literature are examined and new topologies are proposed; all showed state-of-the-art performances in silicon. Novel voltage-conscious circuit concepts generally extendable to other wireless systems are discussed, aiming to demonstrate how analog and RF circuits can be improved effectively in ultra-scaled CMOS technologies using purely circuit-level techniques.

Keywords

Analog Circuits, CMOS, Communication Circuits and Systems, Wireless, Supply Voltage, Radio Frequency (RF) Circuits, Process Reliability

On-Line Short Course in YouTube [~2.5 hours in 7 parts] High-Mixed-Voltage Analog and RF Circuits and Systems for Wireless Applications

(Part 1 of 7) - http://www.youtube.com/watch?v=Vmlbi9aiUFI

(Part 2 of 7) - http://www.youtube.com/watch?v=j9GIa3MDY-U

(Part 3 of 7) - http://www.youtube.com/watch?v=cLxSVvuXdhc

(Part 4 of 7) - http://www.youtube.com/watch?v=FArMd1x-dDU

(Part 5 of 7) - http://www.youtube.com/watch?v=-5k6drS-i-I

(Part 6 of 7) - http://www.youtube.com/watch?v=1xnakUzrywA

(Part 7 of 7) - http://www.youtube.com/watch?v=qH9pfmKLxQo

Slides: https://docs.google.com/file/d/0B-_9DrVl7JtlcWZ1Q2lCNWNRMnc/edit

Learning objectives

Understanding the features, voltage constraints and reliability issues of nanoscale (e.g., 65nm) CMOS technologies

Understanding the system aspects and performance trade-offs of using high-V_DD and mixed-V_DD techniques

Knowledgeable the state-of-the-art high-V_DD and mixed-V_DD circuits via case studies

Capable to Identify novel V_DD-oriented analog and RF circuits for advanced systems

Target audience and prerequisite knowledge of audience

Analog and RF CMOS circuits (low-noise amplifier, mixer, power amplifier, operational amplifier, etc.)

Physical layer of wireless communications (Mobile TV, WLAN, ZigBee, software-defined radios and cognitive radios, etc.)

Books:

Pui-In Mak and R. P. Martins, High-/Mixed-Voltage Analog and RF Circuit Techniques for Nanoscale CMOS, Series of Analog Circuits and Signal Processing (ACSP), Springer Press, Mar. 2012.

SpringerLink: https://link.springer.com/book/10.1007/978-1-4419-9539-1

Preview: http://www.springer.com/engineering/circuits+%26+systems/book/978-1-4419-9538-4

Relevant Journal Papers:

J1. Pui-In Mak and R. P. Martins, “Design of an ESD-Protected Ultra-Wideband LNA in Nanoscale CMOS for Full-Band Mobile TV Tuners,” IEEE Transactions on Circuits and Systems – I, vol. 56, pp.933-942, May 2009. [2010 IEEE CASS Outstanding Young Author Award]

J2. Pui-In Mak and R. P. Martins, “A 2xV_DD-Enabled Mobile-TV RF Front-End with TV-GSM Interoperability in 1-V 90-nm CMOS,” IEEE Transactions on Microwave Theory and Techniques, vol. 58, pp.1664-1676, Jul. 2010.

J3. Pui-In Mak and R. P. Martins, “High-/Mixed-Voltage RF and Analog CMOS Circuits Come of Age,” IEEE Circuits and Systems Magazine, vol. 10, pp. 27-39, Oct.-Dec. 2010.

J4. Pui-In Mak and R. P. Martins, “A 0.46-mm² 4-dB NF Unified Receiver Front-End for Full-Band Mobile TV in 65-nm CMOS,” IEEE Journal of Solid-State Circuits, vol. 46, pp. 1970-1984, Sept. 2011.

J5. Pui-In Mak and R. P. Martins, “Enhanced RFICs in Nanoscale CMOS,” IEEE Microwave Magazine, vol. 13, pp. 80-89, Sept./Oct., 2012.

J6. Pui-In Mak, Miao Liu, Yaohua Zhao and Rui P. Martins, “Enhancing the Performances of Recycling Folded Cascode OpAmp in Nanoscale CMOS through Voltage Supply Doubling and Design for Reliability,” Wiley International Journal of Circuit Theory and Applications, 2013.

J7. Yong Chen, Pui-In Mak, Li Zhang, He Qian and Yan Wang, “A 5^th-Order 20-MHz Transistorized-LC-Ladder LPF with 58.2-dB SFDR, 68-μW/Pole/MHz Efficiency and 0.13-mm² Die Size in 90-nm CMOS,” IEEE Transactions on Circuits and Systems – II, 2013.

Relevant Conference Papers:

C1. Pui-In Mak, Ka-Hou Ao Ieong and R. P. Martins, “An Open-Source-Input, Ultra-Wideband LNA with Mixed-Voltage ESD Protection for Full-Band (170-to-1700 MHz) Mobile TV Tuners,” IEEE International Symposium on Circuits and Systems (ISCAS), pp. 668-671, May 2008.

C2. Pui-In Mak and R. P. Martins, “A 2xV_DD–Enabled TV-Tuner RF Front-End Supporting TV-GSM Interoperation in 90nm CMOS,” in IEEE Symposium on VLSI Circuits (VLSI), Digest of Technical Papers, pp. 278-279, Jun. 2009.

C3. Pui-In Mak and R. P. Martins, “A 0.46mm² 4-dB NF Unified Receiver Front-End for Full-Band Mobile TV in 65nm CMOS,” IEEE International Solid-State Circuits Conference (ISSCC), Digest of Technical Papers, pp. 172-173, Feb. 2011. [Recognized as Chip Olympics]

C4. Liu Mia, Pui-In Mak, Zushu Yan and R. P. Martins, “A High-Voltage-Enabled Recycling Folded Cascode OpAmp for Nanoscale CMOS Technologies,” IEEE International Symposium on Circuits and Systems (ISCAS), pp. 33-36, May 2011.

C5. Zhicheng Lin, Pui-In Mak and R. P. Martins, “A 1.7mW 0.22mm² 2.4GHz ZigBee RX Exploiting a Current-Reuse Blixer + Hybrid Filter Topology in 65nm CMOS,” IEEE International Solid-State Circuits Conference (ISSCC), Digest of Technical Papers, pp. 448-449, Feb. 2013. [Recognized as Chip Olympics]

Relevant Short Courses/Tutorials:

T1. Pui-In Mak, “High-/Mixed-Voltage Analog and RF Circuits and Systems for Wireless Applications,” IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), Taiwan, Dec. 2012.

T2. Pui-In Mak and Rui P. Martins, “High-/Mixed-Voltage Analog and RF Circuits and Systems for Wireless Applications,” IEEE International Symposium on Circuits and Systems (ISCAS), Korea, May 2012.

T3. Pui-In Mak, “High-/Mixed-Voltage Analog and RF Circuit Techniques for Nanoscale CMOS,” IEEE Circuits and Systems Society (CASS) Region-10 Summer School, Taiwan, Aug. 2011.

Relevant Lectures:

L1. Pui-In Mak, “Ultra-Low-Power ZigBee/WPAN Radios in 65nm CMOS,” Hong Kong University of Science and Technology, Hong Kong, China, Jan. 2013.

L2. Pui-In Mak, “High-/Mixed-Voltage Analog and RF Circuit Techniques for Nanoscale CMOS Technologies,” Tsinghua University, Beijing, Nov. 2011.

L3. Pui-In Mak, “High-/Mixed-Voltage Analog and RF Circuit Techniques for Nanoscale CMOS,” State Key Laboratory of Analog and Mixed-Signal VLSI - Science Series/First Distinguished Lectures & Lab Workshop, Macau, Jul. 2011.

L4. Pui-In Mak, “A 0.46mm² 4-dB NF Unified Receiver Front-End for Full-Band Mobile TV in 65-nm CMOS,” University of California Berkeley, USA, Feb. 2011.

L5. Pui-In Mak, “A 0.46mm² 4-dB NF Unified Receiver Front-End for Full-Band Mobile TV in 65-nm CMOS,” IEEE Solid-State Circuits Society Macau Chapter ISSCC Rehearsal, Macau, Jan. 2011.

L6. Pui-In Mak, “High-/Mixed-Voltage Analog and RF Circuit Techniques for Nanoscale CMOS Technologies,” Hong Kong University of Science and Technology, Hong Kong, Nov. 2010.

L7. Pui-In Mak, “High-/Mixed-Voltage Analog and RF Circuit Techniques for Nanoscale CMOS Technologies,” University of Pavia, Italy, Nov. 2010.

L8. Pui-In Mak, “High-/Mixed-Voltage Analog and RF Circuit Techniques for Nanoscale CMOS Technologies,” Tecnologia da Universidade Nova de Lisboa, Portugal, Nov. 2009.

L9. Pui-In Mak, “High-/Mixed-Voltage Analog and RF Circuit Techniques for Nanoscale CMOS Technologies,” Instituto Superior Técnico, Portugal, Nov. 2009.

L10. Pui-In Mak, “A 2xV_DD-Enabled RF Front-End for Mobile-TV Tuners,” Fudan University, Shanghai, May 2009.

Relevant Works (from both academic and industry):

-Mixed-Voltage Mobile-TV Tuner -

R1. J. Greenberg, et al., “A 40MHz-to-1GHz Fully Integrated Multistandard Silicon Tuner in 80nm CMOS,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2012, pp. 162-163.

-High-Voltage Tunable Bandpass Filter-

R2. M. Darvishi, R. van der Zee, E. Klumperink, B. Nauta, “A 0.3-to-1.2GHz Tunable 4^th-Order Switched g_m-C Bandpass Filter With >55dB Ultimate Rejection and Out-of-Band IIP3 of +29dBm,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2012, pp. 358-359.

-Mixed-Voltage Sigma-Delta Analog-to-Digital Converter-

R3. H. Shibata, R. Schreier, W. Yang, A. Shaikh, D. Paterson, T. Caldwell, D. Alldred, P. W. Lai, “A DC-to-1GHz Tunable RF ΔΣ ADC Achieving DR = 74dB and BW = 150MHz at f0 = 450MHz Using 550mW,” in IEEEInt. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2012, pp. 150-151.

-Mixed-Voltage mm-Wave Power Amplifier-

R4. I. Sarkas, A. Balteanu, E. Dacquay, A. Tomkins, S. Voinigescu, “A 45nm SOI CMOS Class-D mm-Wave PA With >10Vpp Differential Swing,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2012, pp. 88-89.

-High-Voltage Class-D Amplifier-

R5. B. Serneels, E. Geukens, B. De Muer, T. Piessens, “A 1.5W 10V-Output Class-D Amplifier Using a Boosted Supply From a Single 3.3V Input in Standard 1.8V/3.3V 0.18µm CMOS,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2012, pp. 94-95.

-Adaptive-Voltage Microprocessor-

R6. S. Luetkemeier, T. Jungeblut, M. Porrmann, and U. Rueckert, “A 200mV 32b subthreshold processor with adaptive supply voltage control,” in ISSCC Dig. Tech. Papers, Feb. 2012, pp. 484–485.

-Mixed-Voltage Software-Defined Radio Receiver-

R7. J. Borremans, G. Mandal, V. Giannini, B. Debaillie, M. Ingels, T. Sano, B. Verbruggen, J. Craninckx, “A 40 nm CMOS 0.4–6 GHz receiver resilient to out-of-band blockers,” IEEE J. Solid-State Circuits, vol. 46, no. 7, pp. 1659–1671, Jul. 2011.

-High-Voltage Class-D Power Amplifier-

R8. H. Xu, Y. Palaskas, A. Ravi, M. Sajadieh, M. A. El-Tanani, and K. Soumyanath, “A flip-chip-packaged 25.3 dBm class-D outphasing power amplifier in 32 nm CMOS for WLAN application,” IEEE J. Solid-State Circuits, vol. 46, no. 7, pp. 1596–1605, Jul. 2011.

-High-Voltage Switched-Capacitor Power Amplifier-

R9. S.-M. Yoo, J. S. Walling, E. C. Woo, and D. J. Allstot, “A switched capacitor power amplifier for EER/polar transmitters,” in ISSCC Dig. Tech. Papers, Feb. 2011, pp. 428–430.

-High-Voltage Current-Mode Lowpass Filter-

R10. A. Pirola, A. Liscidini, and R. Castello, “Current-mode, WCDMA channel filter with in-band noise shaping,” IEEE J. Solid-State Circuits, vol. 45, 9, no. 9, pp. 1770–1780, Sep. 2010.

-Mixed-Voltage GPS Receiver-

R11. H. Moon, S. Lee, S.-C. Heo, H. Yu, J. Yu, J.-S. Chang, S.-I. Choi, and B.-H. Park, “A 23mW fully integrated GPS receiver with robust interferer rejection in 65nm CMOS,” in ISSCC Dig. Tech. Papers, Feb. 2010, pp. 68–69.

-Mixed-Voltage RF Transmitter-

R12. M. Zargari, L. Nathawad, H. Samavati, et al., “A Dual-Band CMOS MIMO Radio SoC for IEEE 802.11n Wireless LAN,” IEEE J. Solid-State Circuits, vol. 43, pp. 2882–2895, Dec. 2008.

-Mixed-Voltage Mobile-TV Tuner -

R13. I. Vassilios et al., “A 65-nm CMOS multistandard, multiband TV tuner for mobile and multi-media applications,” IEEE J. Solid-State Circuits, vol. 43, no. 7, pp. 1522–1533, Jul. 2008.

-Motivation of High-Voltage and Mixed-Voltage Analog Design-

R14. Seyfi Bazarjani, Lennart Mathe, Dana Yuan, Jeff Hinrichs, and Guoqing Miao, "High-Voltage Low-Power Analog Design in Nanometer CMOS Technologies," IEEE Bipolar/BiCMOS Circuits and Technology Meeting (BCTM), 149-154, Sept. 2007.

-High-Voltage Line Driver-

R15. B. Serneels, M. Steyaert, and W. Dehaene, “A 237 mW aDSL2+ CO line driver in a standard 1.2V 130nm CMOS technology,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2007, pp. 524–525.

-Mixed-Voltage Software-Defined Radio Receiver-

R16. R. Bagheri, A. Mirzaei, S. Chehrazi, M. E. Heidari, M. Lee, M. Mikhemar, W. Tang, and A. A. Abidi, “An 800-MHz–6-GHz software-defined wireless receiver in 90-nm CMOS,” IEEE J. Solid-State Circuits, vol. 41, no. 12, pp. 2860–2876, Dec. 2006.

-High-Voltage Operational Amplifier-

R17. K. Ishida, A. Tamtrakarn, and T. Sakurai, “An outside-rail opamp design targeting for future scaled transistors,” in Proc. IEEE Asian Solid-State Circuits Conf. (A-SSCC), Nov. 2005, pp.73–76.

-Motivation of High-Voltage Analog Design-

R18. A.-J. Annema, B. Nauta, R. V. Langevelde, and H. Tuinhout, “Analog circuits in ultra-deep-submicron CMOS,” IEEE J. Solid-State Circuits, vol. 40, pp. 132–143, Jan. 2005.