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Adding Serial Pattern Trigger feature to LOGICPORT

1. Introduction

LogicPort is a pretty good Logic Analyzer to debug the digital system. The only problem I encountered is that it did not provide the Serial Pattern Trigger feature, thus it is actually hard to deal with the complex SPI, I2C bus.

This LA could be used to debug the complex serial bus if it has the serial trigger. As a result, I designed a very simple CPLD board for this Logic Analyzer. The CPLD just mainly used D flip-flops as shift register to convert the serial data to the trigger-able parallel data.

Finally, this idea can add serial trigger to any Logic Analyzer which only provided the parallel trigger feature.


             Sample rate: 0 to 250MHz (clock provided by circuit under test)
       Threshold range: 1.5v, 1.8v, 2.5v, 3.3v

2. Schematic Diagram

(Click to enlarge)

3.RTL View

This design provided 24 bit Serial Pattern Trigger feature by converting serial data to parallel data using D flip-flops, the trigger-able parallel outputs will be generated byte by byte.

4. IO Configuration
& Example

(The trigger condition was "Pattern A is True" and the Pattern A was preset to 802F7Dh)

(Experimental Environment)

    1. Verilog Code
    2. The Gerber file of the PCB
    3. The pof file for MAX II CPLD

Neil Hao,
Aug 8, 2012, 8:29 AM
Neil Hao,
Aug 7, 2012, 3:45 AM
Neil Hao,
Aug 8, 2012, 8:56 AM