Publications

Peer reviewed workshops/conferences/journals

2011

  • Sanghoon Lee, Jeff Danis, James Tuck.  AutoPipe: A Pipeline Parallelization Framework in GCCGROW'2011: Workshop on Research Opportunities in GCC, in conjunction with CGO 2011. 
  • Sanghoon Lee and James Tuck.  Automatic Parallelization of Fine-grained Meta-functions on a Chip Multiprocessor. CGO'11: IEEE/ACM International Symposium on Code Generation and Optimization, April 2011. (pdf)
  • Sanghoon Lee, Devesh Tiwari, Yan Solihin, James Tuck.  HAQu: Hardware Accelerated Queueing For Fine-Grained Threading on a Chip Multiprocessor.   HPCA-17: Proceedings of the 17th IEEE International Symposium on High Performance Computer Architecture, February 2011. (pdf)

2010

  • George Patsilaras, Niket K. Choudhar, James Tuck. Design Trade-offs for Memory Level Parallelism on a Asymmetric Multicore System. PESPMA'10: Third Workshop on Parallel Execution of Sequential Programs on Multi-core Architectures (PESPMA) held in conjunction with ISCA, June 2010. (pdf) (ppt)
  • Liang Han, Wei Liu, James Tuck.  Speculative Parallelization of Partial Reduction Variables, CGO'10: IEEE/ACM International Symposium on Code Generation and Optimization, 2010. (pdf) (ppt)
  • Devesh Tiwari, Sanghoon Lee, James Tuck and Yan Solihin. MMT: Exploiting Fine-Grained Parallelism in Dynamic Memory ManagementIPDPS'10: Proceedings of  24th International Parallel & Distributed Processing Symposium (IPDPS) Track-Software, April 2010. (pdf) (presentation)

2009

  • Devesh Tiwari, Sanghoon Lee, James Tuck, Yan Solihin.  Memory Management Thread for Heap Allocation Intensive Applications.    MEDEA'09: Workshop on Memory Performance (MEDEA), in association with ACM PACT 2009.

2008

  • Sanghoon Lee, James Tuck. Parallelizing Mudflap Using Thread-Level Speculation on a CMP. PESPMA'08: First Workshop on Parallel Execution of Sequential Programs on Multi-core Architectures (PESPMA) held in conjunction with ISCA, June 2008.
  • James Tuck, Wonsun Ahn, Luis Ceze, Josep Torrellas.  Software-Exposed Hardware Signatures for Code Analysis and Optimization. IEEE Micro Magazine Special Issue: Top Picks of 2008 in Computer Architecture Conferences.
  • James Tuck, Wonsun Ahn, Luis Ceze, Josep Torrellas. SoftSig: Software-Exposed Hardware Signatures for Code Analysis and Optimization.  ASPLOS'08: The Thirteenth International Conference on Architectural Support for Programming Languages and Operating Systems, March 2008.

2007

  • James Tuck, Wei Liu, Josep Torrellas . CAP: Criticality Analysis for Power Efficient Speculative Multithreading.
    ICCD'07: The IEEE International Conference on Computer Design (ICCD), Oct. 2007.
  • Luis Ceze, James Tuck, Pablo Montesinos, and Josep Torrellas . Bulk Enforcement of Sequential Consistency. ISCA'07: International Symposium on Computer Architecture, June 2007.

2006

  • James Tuck, Luis Ceze, and Josep Torrellas. Scalable Cache Miss Handling for High Memory Level Parallelism. MICRO'06: International Symposium on Microarchitecture (MICRO), December 2006.
  • Luis Ceze, James M. Tuck, Calin Cascaval, and Josep Torrellas. Bulk Disambiguation of Speculative Threads in Multiprocessors. ISCA'06: International Symposium on Computer Architecture (ISCA), June 2006.
  • Luis Ceze, Karin Strauss, James Tuck, Jose Renau and Josep Torrellas . Using Checkpoint-Assisted Value Prediction to Hide L2 Misses. IEEE Transactions on Architecture and Code Optimization (TACO 2006)
  • Wei Liu, James Tuck, Luis Ceze, Wonsun Ahn, Karin Strauss, Jose Renau and Josep Torrellas . POSH: A TLS Compiler that Exploits Program Structure. PPoPP'06: Principles and Practice of Parallel Programming (PPoPP), March 2006.
  • Jose Renau, Karin Strauss, Luis Ceze, Wei Liu, Smruti Sarangi, James Tuck, and Josep Torrellas. Energy-Efficient Thread-Level Speculation on a CMP. IEEE Micro's Top Picks, January-February 2006.

2005

  • Jose Renau, Karin Strauss, Luis Ceze, Wei Liu, Smruti Sarangi, James Tuck, and Josep Torrellas . Thread-Level Speculation on a CMP Can Be Energy Efficient. ICS'05: ACM International Conference on Supercomputing (ICS), June 2005.
  • Jose Renau, James Tuck, Wei Liu, Luis Ceze, Karin Strauss, and Josep Torrellas . Tasking with Out-of-Order Spawn in TLS Chip Multiprocessors: Microarchitecture and Compilation. ICS'05: ACM International Conference on Supercomputing (ICS) , June 2005.

Posters and Technical Reports

  • Sanghoon Lee, Devesh Tiwari, Yan Solihin, James Tuck. Parallelization of Mudflap on a Chip Multiprocessor. Technical Report, July 2009.
  • Rajesh Vanka and James Tuck, Poster: Improving MemoiSE via Function Splitting,  Poster session at PACT'09.
  • Sethuraman Gopal and James Tuck, A Data Dependence Profiler for the GNU Compiler Collection,  December 2008.
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