Projects

Funded Projects

Exploring Helper Computing Parallelism on Multicore Architectures 

Sponsored by the National Science Foundation.
Co-PI: Prof. Solihin

The project seeks to develop helper computing technology for enhancing reliability and security of computer systems. As software complexity increases and threats from security attacks grow, a new low-overhead approach for improving software reliability and security is urgently needed. In helper computing, relatively autonomous ``helper'' threads or processes execute extra code on behalf of the application on separate processors or thread contexts. In the past, the use of helper threads was constrained to prefetching and branch prediction. In this project, we propose exploring a new and novel use of helper computing for improving software reliability and security. With helper computing, reliability and security functionalities that are normally performed as parts of the application code are off- loaded to the helper thread/process. This enables sophisticated functionalities to be computed in parallel with the application without slowing down the application much.


Software Exposed Hardware Signatures for Code Analysis, Optimization, and Debugging


Sponsored by the National Science Foundation.

Effective dynamic memory disambiguation limits many practical approaches for code analysis, optimization, and debugging. A potential avenue for overcoming the traditional limits of hardware memory disambiguation is through the use of signature registers. Such registers can operate on hundreds of addresses simultaneously. Such registers can be exposed to software through a flexible and general interface for use in a wide variety of systems. However, because signatures represent sets of addresses imprecisely, they are prone to false positives which limit their accuracy and effectiveness. This research will investigate the effectiveness of exposing signature registers to software.


Projects Under Development


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