Projects


ScanLife


Develop, debug, and manage a mobile software application, ScanLife, at Scanbuy Inc., in C++ on camera phones, which is used to scan 1D/2D barcodes, decode images, connect to server and launch a browser, on Visual Studio based BREW SDK framework for running simulators and use Windows NMAKE and ARM compiler to compile and run the app on BREW devices



Augmented Reality Electronic Field Guide


We develop a tangible augmented reality 3D user interface to assist field botanists in identifying and collecting plant specimens.
This project is implemented in C# with GoblinXNA.



Augmented Reality Shaking Menu

We develop an augmented reality 3D shaking menu technique. The shaking of the hand-held fiducial can be detected in several kinds of directions: horizontal (x-axis) movements, vertical (y-axis) movements, rotative movements, and forward and backward (z-axis) movements. Shakings can be detected by a series of four repeated movements. After the shaking is detected, the menu will appear. Then wait for 2 seconds, the menu will be fixed and placed by one of four kinds techniques: the display-fixed, the object-fixed, the world-fixed, and the clipboard-fixed. Then users can move the fiducial over each the menu to select one of them. We use ray-casting technique to detect the intersection between an invisible ray and objects to detect the selection. When one menu object is overlaid, it will flash to notify the user that it is detected. After 3 seconds of flashing, the menu object will be selected. The 3 seconds allow users to make mistakes and change their selection. We did a user study on those four kinds of selection techniques.
This project is implemented in C# with GoblinXNA.
This paper was published on ISMAR 2009, Florida. Here is a demo video of shake menu.

YouTube Video

Here is another review:



Augmented Reality Manhattanville Project

We develop an augmented reality 3D user interface to create situated visualizations that overlay an architectural site with information for users to observe and explore. This site is called "Manhattanville" which is located between 125th street, 133rd street, Broadway, and Riverside Drive on the upper west of Manhattan Island. We created a "Golden Finger" which can detect the specific building that it overlays by casting a ray from "eye" to infinity and detecting the intersection. When the building is detected, it will flash to notify users. We also created a special cylinder tool bar to select menus in different hierarchies. Based on the specific menu function selected, different information will be shown on the screen. Therefore, all the building information can be visualized in an easy way by operating our tool bar, "Golden Finger" and menus.
This project is implemented in C# with GoblinXNA.



Ray Tracer


Ray tracer is a technique for generating stunning images for 3D models. To be simple, a ray tracer traces the path of light through each pixel in an image plane and tries to find out the precise color for the pixel. The advantage of ray tracer is that it can give us a photo-like image of anything we can think of (and of course, we have to create it in a 3D scene). We built this program with the functions: ray-surface interaction tests, lighting and shadows, recursive mirror reflections and recursive refractions. For more information about ray tracing, take a look at Wiki.
This project is implemented in C++ with OpenGL.



==miniQuake==

This is a little 3D area scene we built that looks like the game "Quake", so we call it "==miniQuake==". It's basically just a practice of OpenGL scenery. Users can walk around in the arena, look up and down, turn on/off the light, etc. There are two cute little robots running around and a huge monster imported from a Maya 3D model standing in the arena. For more details, please check our project website, or download the game and try yourself!
This project is implemented in C++ with OpenGL.



Coons Patch

Coons Patch is a technique that forms a Bezier patch from 4 lines connected by their end points in Computer Aid Geometry Design (CAGD). The basic idea is that we are given the four boundary Bezier curves for a patch (two curves of degree n, and two curves of degree m). Then we use these 4 curves to determine the interior control points to make a rectangular array of (m+1) * (n+1) points (rows * columns), from which we can then evaluate (by a u, v pair) to get a point on the surface. Since, for the array of size (m+1) * (n+1), we are given the first and last points in every row and column (which are given by the boundary curves), we only have determine the interior (m-1) * (n-1) points. The (m-1) * (n-1) points can be determined by a blend of two linear interpolations and one bilinear interpolation. Once we've computed the interior points, we can evaluate the Coons Patch as a tensor product surface, i.e., treat the (m+1) rows as Bezier curves in u and evaluate them individually, then use the m+1 resulting points as the control points for a Bezier curve and evaluate that according to v. In this manner we use the result of a Bezier curve evaluation to do surface evaluation. The Bezier curve can be evaluated by the de Casteljau algorithm.
This project is implemented in Java with Java Applet.



Parallel Implementation on Evaluating "Coons Patch" by using PThread

This project is to implement the parallel version of evaluating Coons patch. Since the runtime of the evaluation of Coons patch becomes very large when the u, v parameters are huge, there is a need to speed up the computation process to achieve real time rendering when requiring huge surface points. There are two stages of processes need to be paralleled. The 1st stage is the computation of interior control points. The 2nd stage is the evaluation of tensor product surface. I use the PThread programming model to implement this parallel version process, since PThread is a shared memory model that is suitable for this application. There are two barriers, which are the synchronization points in this process. The 1st one is at the end of the 1st stage to make sure all the threads finish its calculation of interior control points, and the 2nd one is at the end of the 2nd stage to make sure all the threads finish its evalution of tensor product surface. The simulation results show that the 1st stage is a fine-grained stage, and the 2nd stage is a coarse-grained stage. The loadings of each thread are balanced. It also shows that the decrease of runtime with the increase of number of threads, which means the speed increases with scaling. It also shows the granularity increases with the increase of number of threads, which means the computation to communication ratio increases with scaling.
This project is implemented in C++ with PThread and OpenGL on Linux platform.



Black Jack

This project is to implement an online gaming software system, the "Black Jack", which allows multiple players to simultaneously login and play cards together by using component model framework. Client players can interact with web pages to login/logout, and play game. The pages will request service via JSP from EJB application server, and respond back to the users. When application server received requests from clients, it will find the EJB instances, and call the corresponding interface, and put the feedback back to clients. The Java Beans will provide card shuffling, distribution , winner strategy and user management functions; they will also interact with database to make query and updates user information, like name, password, money, etc. We have implemented several functions. For an administrator, the functions are "Login", "Create User", "Modify User", "Delete User", and "Logout". For a player, the functions are "Login", "Join Table", "Set Ready", "Card Bid", "Card Hit", "Card Stand", "Double Down", and "Logout". We use GWT (Google Web Toolkit) to develop our front end user interface since it provides a java developing environment and powerful functions.
This project is implemented in Java with GWT, EJB3, and MySQL.



A Real-Time Image Processing System-on-a-Chip for DNA Microarray

DNA Microaray Image promises to monitor the whole genome on a single chip so that researchers can have a better picture of the interaction among thousands of genes simultaneously. The microarray image reveals a fluorescent mosaic of spots, each one representing the matching degree of a pair of genetic strands: their color indicate which bases have joined, while the intensities of the red, green, and yellow represent the hybridization degree of one, the other, or both of the target DNAs. This project is to implement the microarray image analysis hardware to speed up the the process of the fluorescence images. We propose a 8-bit CISC microprocessor integrated with image spatial filter silicon IPs as a SoC for real-time DNA microarray image pre-processing. We use the component-wise scheme to perform two channel color image filtering. Two methodologies based on the Real-Time Image Processing SoC (RTIPS) is proposed to generate R-G channel spot map and edge map with clear background and obvious spot contour and edge contour to speed up genome analysis. The first one is to acquire the intensity images with clear background and obvious spot contour for spot intensity analysis with various thresholds. The second one is to acquire the gradient image with clear background and obvious edge contour for spot edge analysis with various thresholds.
The full article of my M.S. thesis can be downloaded here.



Real-Time Image Processing Unit

This Real-Time Image Processing Unit (RTIPU) is implemented by integrating a refined 8-bit CISC microprocessor with 8 image spatial filters and 4 morphological operators. Two external memory banks are employed to store the unprocessed and processed images, which support 4 kinds of memories: ROM, EEPROM, SRAM, and Flash ROM. The 8-bit CISC microprocessor is 2-stage pipelined. The instructions are compatible to Intel MCS-51 Family. There are 49 Special Function Registers (SFR) in RTIPU, where 21 SFRs are the same as standard Intel i8051, and extra 28 SFRs are designed to accommodate the integrated 8 image spatial filters and 4 morphological operators. A dual-clock-rate strategy (the clock rate in certain modules is half of the others') is applied to solve the problem of reading from and writing to external memories via a single address bus. The component-wise scheme is used to perform three channel (R, G, B) color image filtering. The maximum operating frequency of RTIPU can be achieved at 333 MHz, e.g., 2540 frames per second for 256x256 images and the total equivalent gate count of RTIPU is 441246, e.g., 4412464 um^2.
This project is implemented in Verilog by using Xilinx Foundation, its FPGA board, and Cadence's Verilog-XL



VLSI Implementation of ADM Edge Detection Algorithm

The ADM (Absolute Difference Mask) algorithm is a low-computational-complexity algorithm especially suitable for hardware implementation for edge detection, which can be divided into 3 stages: "Semi-Gaussian Smoothing", "Edge Strength and Direction Calculation", and "Edge Localization". This ADM VLSI implementation is integrated in the Real-Time Image Processing Unit (RTIPU) as a part of low level image processing filters. The component-wise scheme is used to process color images.
This project is implemented in Verilog by using Xilinx Foundation, its FPGA board, and Cadence's Verilog-XL



VLSI Implementation of Low Level Spatial Image Processing Filters

This project is to implement 7 kinds of linear and non-linear image filter silicon IP and 4 kinds of morphological image filter IP. We also integrate those filters with a 6-clock-cycle FIFO (6CFIFO) and design the interface to support 4 kinds of memory: ROM, SRAM, flash ROM and EEPROM. The latency of The 7 kinds of image spatial filters (7SF) include "Weight Average Operation", "Mean Operation", "Roberts Edge Detection", "Prewitt Edge Detection", "Sobel Edge Detection", "Laplacian Edge Detection", and "ADM Edge Dection". The 4 kinds of morphological image filters include "Erosion", "Dilation", "Open", and "Close". There are totally 4 scalable FIFOs which support 5 different image sizes: 32x32, 64x64, 128x128, 256x256, and 512x512.
This project is implemented in Verilog by using Xilinx Foundation, its FPGA board, and Cadence's Verilog-XL



Low Pass Filter

We design a low pass filter by using a self-biased leveraged current op amp. The leveraged current mirror op amp is achieved by adding a pair of fixed current sources that allows reduced operating-point current in the output stage, while the resulting "leveraging" effect increases slew rate. For equal total power dissipation, the new configuration improves DC gain and gain-bandwidth over conventional current-mirror and folded cascade op amps. The simulation results show that the required specification of the leverage current mirror op amp and the low pass filter are met. The leveraged current mirror op amp is superior to the conventional current mirror op amp and the folded cascode current mirror op amp in slew rate, trnasconductance, and gain. This low pass filter work normally with the change of temperature, the small change of supply voltage and the change of input common mode voltage.






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