LEE JONG MIN

RESEARCH INTERESTS

• Computer Architecture

Processor architectures, Memory architecture, Embedded systems

• High Performance Computing

Performance/Power-aware system management, High performance Processor/Memory, Emerging memories

• Data Analysis

Massive Data Processing, Feature extraction, Machine learning

• System Software

Operating System, Software/Hardware-aware System

CURRICULUM VITAE

• Department of Computer Engineering at Wonkwang University

Assistant Professor, Mar. 2018 ~ 현재

• SW Value Diffusion Center, National Program of Excellence in Software, Wonkwang University

Center Chief, Sep. 2019 ~ Feb. 2022

• DRAM Design Team, Memory Division, Samsung Electronics

Senior Engineer (CL3), Feb. 2015 ~ Mar. 2018

• Department of Computer Science at Korea Advanced Institute of Science and Technology (KAIST)

Integrated M.S/Ph.D in Computer Science, Feb. 2008 ~ Feb. 2015

• Department of Computer Engineering at Dankook University

B.S. in Computer Engineering, Feb. 1999 ~ Feb. 2008

PUBLICATION

International Publications

• "Application-specific Feature Selection and Clustering Approach with HPC System Profiling Data", Mincheol Shin, Geunchul Park, Chan Yeol Park, Jongmin Lee, Mucheol Kim, The Journal of Supercomputing, 2021.

• "Roofline-based Data Migration Methodology for Hybrid Memories", Jongmin Lee, Kwangho Lee, Mucheol Kim, Geunchul Park and Chan Yeol Park, Journal of Internet Technology, Vol. 21, No. 3, pp. 855-865, Jun. 2020.

• "Index-based Activate Operation for High Density DRAMs", Kwangho Lee and Jongmin Lee, IEEE Eurasia Conference on IOT, Communication and Engineering, Oct. 3-6, Taiwan, 2019

• "Improving Hybrid Memory Usages Through Bandwidth-aware Data Migration Methodology", Kwangho Lee and Jongmin Lee, International Conference on Platform Techonology and Service (PlatCon), Jan. 28-30, Korea, 2019

• "PCA based Performance Analysis with System Profiling Data in Many-core System", Mucheol Kim, Junho Kim, Jongmin Lee, Geunchul Park, and Chanyeol Park, The International Conference on Recent Advancements in Computing, IoT and Computer Engineering Technology, Taiwan, Oct. 29~31, 2018

• "TLB Index-based Tagging for Reducing Data Cache and TLB Energy Consumption", Jesung Kim, Jongmin Lee, and Soontae Kim, IEEE Transactions on Computers (TC), Vol. 66, No. 7, pp. 1200-1211, Jul. 2017.

• "A Way-Filtering-Based Dynamic Logical-Associative Cache Architecture for Low-Energy Consumption", Jungwoo Park, Jongmin Lee, and Soontae Kim, IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol. 25, No. 3, pp. 793-805, Mar. 2017.

• "Write Buffer-Oriented Energy Reduction in the L1 Data Cache for Embedded Systems", Jongmin Lee and Soontae Kim, IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol. 24, No. 3, pp. 871-883, Mar. 2016.

• "Filter Data Cache: An Energy-Efficient Small L0 Data Cache Architecture Driven by Miss Cost Reduction", Jongmin Lee and Soontae Kim, IEEE Transactions on Computers (TC), Vol. 64, No. 7, pp. 1927-1939, Jul. 2015.

• "Ternary Cache: Three-valued MLC STT-RAM Caches", Seokin Hong, Jongmin Lee, and Soontae Kim, IEEE International Conference on Computer Design (ICCD'14), Seoul, Korea, Oct. 19-22, 2014. (63 papers accepted out of 202 submissions, 31% acceptance rate, Best Paper Nominee)

• "Skinflint DRAM System: Minimizing DRAM Chip Writes for Low Power", Yebin Lee, Soontae Kim, Seokin Hong, and Jongmin Lee, IEEE International Symposium on High Performance Computer Architecture (HPCA'13), Feb. 23-27, 2013, Shenzhen, China (51 papers accepted out of 249 submissions, 20% acceptance rate)

• "Adopting TLB Index-based Tagging to Data Caches for Tag Energy Reduction", Jongmin Lee and Soontae Kim, ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED’12), California, USA, Jul. 30 ~ Aug. 1, 2012 (66 papers accepted out of 213 submissions, 31% acceptance rate).

• "Residue Cache: A Low-Energy Low-Area L2 Cache Architecture via Compression and Partial Hits", Soontae Kim, Jesung kim, Jongmin Lee, and Seokin Hong, In Proc. of IEEE/ACM International Symposium on Microarchitecture (Micro’11), Dec. 3~7, 2011, Brazil (44 papers accepted out of 209 submissions, 21% acceptance rate).

• "TLB Index-based Tagging for Cache Energy Reduction (long paper)", Jongmin Lee, Seokin Hong, Soontae Kim, ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED’11), Fukuoka, Japan, Aug. 1~3, 2011 ( 30 long papers, 45 regular papers accepted out of 201 submissions, 14.9% and 22.4% acceptance rates, respectively).

• "Write buffer-oriented energy reduction in the data cache of two-level caches for the embedded systems", Soontae Kim and Jongmin Lee, ACM Great Lakes Symposium on VLSI (GLSVLSI’10), Providence, USA, May 16~18, 2010. (50 regular papers accepted out of 165 submissions, 30% acceptance rate)

• "Energy-delay efficient 2-level data cache architecture for embedded systems", Jongmin Lee, Soontae Kim, In Proc. of ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED’09), San Francisco, CA, USA, Aug. 2009 (75 papers accepted out of 210 submissions, 35.7% acceptance rate).

Domestic Publications

• "Small Active Command Design for High Density DRAMs", Kwangho Lee and Jongmin Lee, Journal of KSCI, Nov., 2019.

• "Bandwidth-aware Memory Placement on Hybrid Memories targeting High Performance Computing Systems ", Jongmin Lee, Journal of KSCI, Aug., 2019.

• "Energy-delay efficient 2-level data cache architecture for embedded system", Jongmin Lee and Soontae Kim, Journal of KIISE, Oct., 2010.

• "Low-Power 2-level Cache Architectures for Embedded system", Jongmin Lee and Soontae Kim, KIPS Fall Conference, 2008.

PATENTS

International

• Apparatus for Migration data and Method of Operating Same, (2019 미국 출원)

Domestic

• 스몰 액티브 커맨드를 이용한 메모리 시스템 (2021 등록, 제 10-2343550호)

• 데이터이주장치 및 그 동작 방법, (2020 등록, 제 10-2089450호)