SPI - Serial Peripheral Interface
The Serial Peripheral Interface Bus or SPI bus is a synchronous serial data link standard which opererate in a full duplex mode. Devices communicate in master or slave mode where the master device initiates the data frame. Multiple slave devices are allowed with individual slave select lines with the chip select.
The following are the SPI bus logic signals, which in all it has four. These are:
SCLK — Serial Clock (output from master)
MOSI/SIMO — Master Output, Slave Input (output from master)
MISO/SOMI — Master Input, Slave Output (output from slave)
SS — Slave Select (active low; output from master)
Other short convention names are explained below.
SCLK — Serial Clock (output from master)
SDI — Serial Data In
SDO — Serial Data Out
CS — Chip Select (active low; output from master)
The SPI bus can operate with a single master device only and with one or more slave devices connected wth tne master device. If a single slave device is used, the SS pin has to be connected logic low. This because the slaves require the falling edge (from high to low state transistion) of the slave select. The following picture describe how a single master and a single slave can be connected togheter, with all the pins needed.
With multiple slave devices, an independent SS signal is required from the master for each slave device. So if there are 4 slave connected to the master, there has to be 4 SS pins on the master so that they can be connected. The following picture shows how a single master and 3 slaves can be connected together with all the pins shown.
1) The first thing to do to begin a communication between the master and the slave is that, the master need to sets the slave select low for the desired chip (either SS1 or SS2 ect..).Advantages:
2) After this step the master need to wait for some period of timesince the slave have some time delay convertion.
3) The master then generates a clock frequency less than or equal to the maximum frequency the slave device supports. The clock frequecny is usually configured on the master side.
4) During clock generation, a full duplex transmission occurs:
>> the master sends data on the MOSI line; the slave reads from the MOSI line
>> the slave sends data on the MISO line; the master reads from the MISO line
>> Full duplex communication for higher throughputDisadvantages:
>> Higher throughput than I²C
>> No addressing means reduced overhead which can be advantageous in small number (if not single) slave.
>> Requires more pins on IC packages:
>> No addressing requires chip selects
>> No hardware flow control
>> No slave acknowledgment (the master could literally be "talking" to nothing and not know it)
I²CI²C is a multi-master serial computer bus invented by Philips that is used to attach low-speed peripherals to a motherboard, embedded system, or cellphone. The figure below shows how circuit with one master (a microcontroller) and three slaves like ADC, a DAC, and another microcontroller with pull-up resistors Rp.Design:
I²C uses only two bidirectional open-drain lines, serial data (SDA) and serial clock (SCL), pulled up with resistors. Typical voltage of the system varies between +3.3V to +5 V. The I²C reference design has a 7-bit address space with 16 reserved addresses, so a maximum of 112 nodes can communicate on the same bus. The common data rate for I²C bus modes are the 100 Kbit/s (standard) and the 10 Kbit/s (low-speed), even with a clock frequency of zero are also allowed. Recent I²C can host more nodes and run faster with a clock frequency of 400 Kbit/s (Fast speed) and 3.4 Mbit/s (High Speed).
Communication and Connection:
The communication and connection between the master and the slave, is a bus with a clock (SCL) and data (SDA) lines with 7-bit addressing with a 1-bit at the beginning (start bit) and a 1-bit at the end (stop bit). The bus has two types of nodes: master and slave:
>> Master node — node that controls the clock
>> Slave node — node that is not in control of the clock line.
The bus is a multi-master bus which means any number of master nodes can be present. Additionally, a master can also be a slave, and vice-versa.
Overall, there are four distinct modes for a given bus:
>> master transmit — the node is in control of the clock and is sending data to a slave
>> master receive — the node is in control of the clock but is receiving data from a slave
>> slave transmit — the node is not in control of the clock but is sending data to a master
>> slave receive — the node is not in control of the clock but is receiving data from the master
As shown on the next figure, the master begins the communication by issuing the start condition (S). The master continues by sending a unique 7-bit slave device address, with the most significant bit (MSB) first. The eighth bit after the start, read/not-write (), specifies whether the slave is now to receive (0) or to transmit (1). An ACK bit issued by the receiver, acknowledging receipt of the previous byte, follows this. Then the transmitter (slave or master, as indicated by the bit) transmits a byte of data starting with the MSB. At the end of the byte, the receiver (whether master or slave) issues a new ACK bit. This 9-bit pattern is repeated if more bytes need to be transmitted.
The following points give a clear idea of what master or the slave has to do when to read or write:
>> Master Write to the Slave: Repeatedly sends a byte with the slave sending an ACK bit. (The master has to be transmitting mode and the slave in slave receive mode.)
>> Master Read from the Slave: Repeatedly receives a byte from the slave, the master sending an ACK bit after every byte but the last one.
>> Master Ends Transmission by sending a stop bit
>> Master retain control of the bus by sending a START bit
The following circuit gives an idea of the resistors values and the connections between the master and the slaves connected with it.