Taehoon Kim

Ph.D. student in School of Computing KAIST
Computer Architecture Lab.

Contact Information




Research Interest
I am interested in emerging memory systems and hardware security. I have been working on reducing the
performance degradation of processor security supports. I am working on finding interesting issues and solutions when
adopting data security in emerging memory architectures such as 3D-stacked DRAM and NVRAM.

Publication
  • Taehoon Kim, Joongun Park, Jaewook Woo, Seungheun Jeon, and Jaehyuk Huh, "ShieldStore: Shielded In-memory Key-value Storage with SGX", accepted for the European Conference on Computer Systems (EuroSys), 2019
  • Insu Jang, Adrian Tang, Taehoon Kim, Simha Sethumadhavan, and Jaehyuk Huh, "Heterogeneous Isolated Execution for Commodity GPUs", accepted for the International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), 2019
  • Taehoon Kim, Joongun Park, Jaewook Woo, Seungheun Jeon, and Jaehyuk Huh, "Secure In-memory Key-Value Storage with SGX (Poster)", in The 9th ACM Symposium on Cloud Computing(SoCC), October 2018
  • Seikwon Kim, Seonyoung Lee, Taehoon Kim, and Jaehyuk Huh, “Transparent Dual Memory Compression Architecture,” in The 26th International Conference on Parallel Architectures and Compilation Techniques(PACT), September 2017 [PDF]
  • Junghoon Lee, Taehoon Kim, and Jaehyuk Huh, "Dynamic Prefetcher Reconfiguration for Diverse Memory Architectures", The 34th IEEE International Conference on Computer Design(ICCD), October 2016 [PDF]
  • Junghoon Lee, Taehoon Kim, and Jaehyuk Huh, "Reducing the Memory Bandwidth Overheads of Hardware Security Support for Multi-core Processors", IEEE Transactions on Computers(TC) 65 (11), November 2016 [LINK]
Research Experiences
  • Secure Key-value Store with Intel SGX
    • Proposed a secure key-value store with Intel SGX, alleviating the limitation of SGX.
    • Exploiting a hash-based index structure, ShieldStore proposes efficient fine-grained data protection.
    • Published in SoCC 2018 as a poster and will appear in EuroSys 2019
  • Stacked DRAM with Security Attacks
    • The purpose of this research is to reduce the performance degradation for protecting data and address against malicious security attacks.
    • Using the advantages of stacked DRAM, I expect that secure processor can have moderate performance with data security.
    • On-going work
  • Dynamically Reconfigure Prefetcher for Diverse Memory Architectures
    • Proposed a prefetcher which can be reconfigured according to diverse memory architectures and applications.
    • For hybrid memory, prefetcher can generate prefetch requests according to each memory characteristic.
    • Published in ICCD 2016
  • Reducing the Memory Bandwidth Overheads of Multi-Core Secure Processors
    • Introduced the performance degradation of multi-core secure processors due to the increasing number of memory requests to be protected.
    • Propose efficient memory scheduling and mapping scheme for managing data and metadata in order to improve memory bandwidth utilization.
    • Published in TC 2016
SKILLS 
  • Programming Languages
    • C/C++, Python
  • Simulators & Tools
    • Gem5, McSimA+
    • DRAMSim2, Usimm
  • Hardware Security
    • Secure Processors
    • Intel SGX(Software Guard Extensions)
Education
  • Ph.D. student in School of Computing, KAIST, Feb. 2014 ~ present (Advisor: Jaehyuk Huh
  • M.S. in Department of Computer Science, KAIST, Feb. 2014 (Advisor: Jaehyuk Huh)
  • B.S. in Computer Science, Sogang University, Feb. 2012
Internship
  • Microsoft Research Asia, Sep. 2017 ~ Dec. 2017 (Mentor: Jinglei Ren)
Teaching Assistant
  • CC510 TA Introduction to Computer Application(Spring 2016)
  • CS311 TA Computer Organization(Fall 2015)
  • CS510 TA Computer Architecture(Spring 2015)
  • CS211 TA Digital Systems(Spring 2014)
  • CS500 TA Algorithm(Spring 2013)
  • CS322 TA Formal Language and Automata(Fall 2012)