Taehoon Kim

Taehoon Kim

Senior Researcher at ETRI

Contact Information

E-mail: taehoon.kim@etri.re.kr

                 thkim@casys.kaist.ac.kr

Github repo: https://github.com/cocoppang

Research Interest

I am interested in emerging memory systems and hardware security. I have been working on reducing the performance degradation of processor security supports. I am working on finding interesting issues and solutions when adopting data security in emerging memory architectures such as 3D-stacked DRAM and NVRAM.

International Publication

• Joongun Park, Seunghyo Kang, Sanghyeon Lee,  Taehoon Kim, Jongse Park, Youngjin Kwon, and Jaehyuk Huh, "Hardware Hardened Sandbox Enclaves for Trusted Serverless Computing," ACM Transactions on Architecture and Code Optimization (TACO), 2023

• Taehoon Kim, Kwangwon Koh, Changdae Kim, Eunji Pak, Yeongjeong Jeong, and Sang-Hoon Kim, "DEHype: Retrofitting Hypervisors for a Resource-Disaggregated Environment," The IEEE International Conference on Cluster Computing (CLUSTER), October 2023

• Changdae Kim, Kwangwon Koh, Taehoon Kim, Daegyu Han, and Jiwon Seo, "BWA-MEM-SCALE: Accelerating Genome Sequence Mapping on Commodity Servers," International Conference on Parallel Processing (ICPP), August 2022 (Best Paper Award)

• Joongun Park, Naegyeong Kang, Taehoon Kim, Youngjin Kwon, and Jaehyuk Huh, "Nested Enclave: Supporting Fine-grained Hierarchical Isolation with SGX," The 47th International Symposium on Computer Architecture (ISCA), May 2020 [PDF]

• Insu Jang, Adrian Tang, Taehoon Kim, Simha Sethumadhavan, and Jaehyuk Huh, "Heterogeneous Isolated Execution for Commodity GPUs," The International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), April 2019 [PDF]

• Taehoon Kim, Joongun Park, Jaewook Woo, Seungheun Jeon, and Jaehyuk Huh, "ShieldStore: Shielded In-memory Key-value Storage with SGX," The 14th European Conference on Computer Systems (EuroSys), March 2019 [PDF]

• Taehoon Kim, Joongun Park, Jaewook Woo, Seungheun Jeon, and Jaehyuk Huh, "Secure In-memory Key-Value Storage with SGX (Poster)," The 9th ACM Symposium on Cloud Computing (SoCC), October 2018

• Seikwon Kim, Seonyoung Lee, Taehoon Kim, and Jaehyuk Huh, “Transparent Dual Memory Compression Architecture,” The 26th International Conference on Parallel Architectures and Compilation Techniques (PACT), September 2017 [PDF]

• Junghoon Lee, Taehoon Kim, and Jaehyuk Huh, "Dynamic Prefetcher Reconfiguration for Diverse Memory Architectures," The 34th IEEE International Conference on Computer Design (ICCD), October 2016 [PDF]

• Junghoon Lee, Taehoon Kim, and Jaehyuk Huh, "Reducing the Memory Bandwidth Overheads of Hardware Security Support for Multi-core Processors," IEEE Transactions on Computers (TC) 65 (11), November 2016 [LINK]

Domestic Publications (In Korean)

• 용예원, 김창대, 김태훈, "분리 메모리 시스템의 보안 기술 연구 동향," The Korea Institute of Information Security and Cryptology (KIISC), vol. 33, no 5, pp. 17-24, 2023 [LINK]

Research Experiences

• Performance Optimization for Disaggregated Memory Systems

  • Retrofit hypervisors for a disaggregated memory system

  • Exploiting a large I/O and management units and make hypervisors more disaggregated system-aware

  • Published in CLUSTER 2023

• Secure Key-value Store with Intel SGX

  • Proposed a secure key-value store with Intel SGX, alleviating the limitation of SGX.

  • Exploiting a hash-based index structure, ShieldStore proposes efficient fine-grained data protection.

  • Published in SoCC 2018 as a poster and published in EuroSys 2019

• Stacked DRAM with Security Attacks

  • The purpose of this research is to reduce the performance degradation for protecting data and address against malicious security attacks.

  • Using the advantages of stacked DRAM, I expect that secure processor can have moderate performance with data security.

  • On-going work

• Dynamically Reconfigure Prefetcher for Diverse Memory Architectures

  • Proposed a prefetcher that can be reconfigured according to diverse memory architectures and applications.

  • For hybrid memory, prefetcher can generate prefetch requests according to each memory characteristic.

  • Published in ICCD 2016

• Reducing the Memory Bandwidth Overheads of Multi-Core Secure Processors

  • Introduced the performance degradation of multi-core secure processors due to the increasing number of memory requests to be protected.

  • Propose efficient memory scheduling and mapping scheme for managing data and metadata in order to improve memory bandwidth utilization.

  • Published in TC 2016

Skills

• Programming Languages

  • C/C++, Python

• Simulators & Tools

  • Gem5, McSimA+

  • DRAMSim2, Usimm

• Hardware Security

  • Secure Processors

  • Intel SGX (Software Guard Extensions)

Education and Employment

• Electronics and Telecommunications Research Institute

  • Senior Researcher, Future Computing Research Division, March 2022 ~ Present

  • Researcher, Future Computing Research Division, March. 2020 ~ Feb. 2022

• Ph.D. in School of Computing, KAIST, Feb. 2020 (Advisor: Jaehyuk Huh) 

  • Dissertation: Scalable Persistent Data Protection with Hardware-Trusted Execution

• M.S. in Department of Computer Science, KAIST, Feb. 2014 (Advisor: Jaehyuk Huh)

  • Thesis: Memory Scheduling Techniques for Multi-core Secure Processors

• B.S. in Computer Science, Sogang University, Feb. 2012

Internship

• Microsoft Research Asia, Sep. 2017 ~ Dec. 2017 (Mentor: Jinglei Ren)

Teaching Assistant

• CC510 TA Introduction to Computer Application(Spring 2016)

• CS311 TA Computer Organization(Fall 2015)

• CS510 TA Computer Architecture(Spring 2015)

• CS211 TA Digital Systems(Spring 2014)

• CS500 TA Algorithm(Spring 2013)

• CS322 TA Formal Language and Automata(Fall 2012)