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First of all: welcome to my website. Please navigate in the main menu to get information about certain "hot topics" in the world of electronics.

This site is hosted by mean of 2 url's: http://www.fpga.be and http://www.vhdl.eu .

The main interest of this website is to publish information about FPGAs. FPGAs (Field Programmable Gate Arrays) are one of the products in every system engineer's magic toolbox. FPGAs have been used by engineers worldwide for many years to rapidly prototype systems or meet low-volume preproduction requirements.

At the moment much electronic company's are trying to choose for a solution that has the smallest bill-of-materials. They are looking for silicon solutions that offer low unit and low total system costs.

ASICs (Application Specific Integrated Circuits) and structured arrays have in the past offered the lowest unit cost of any silicon solution in high volume productions. But another problem today is that the time-to-market has to be very short, this fenomenon is exponentially increasing the nonrecurring engineering (NRE) charges. 

But what is an FPGA?

An FPGA is an integrated circuit that contains many identical logic cells that can be viewed as standard components. Each logic cell can independently take on any of alimited set of personalities. The individual cells are interconnected by a matrix of wires and programmable switches. A user's design is implemented by specifying the simple logic function foreach cel and selectively closing the switches in the interconnect matrix. Complex designs are created by combining these basic blocks to create the desired circuit. Field Programmable means that the FPGA's function is defined by a user's program rather than by the manufacturer of the device. Depending on the particular device, the program is either 'burned' inpermanently or semi-permanently as part of a board assembly proces, or is loaded from an external memory each time the device is powered up. The FPGA has three major configurable elements: configurable logic blocks (CLBs), input/output blocks and interconnects.  The CLBs provide the functional elements for constructing user's logic. The IOBs provide the interface between the package pins and internal signal lines. The programmable interconnect resources provide routing paths to connect the inputs and outputs of the CLBs and IOBs onto the appropriate networks. The Field-Programmable Gate Arrays (FPGAs) provide the benefits of custom CMOS VLSI, while avoiding the initial cost, time delay and inherent risk of a conventional masked gate array. The FPGAs are customized by loading configuration data into the internal memory cells. Complex Programmable Logic Devices (CPLDs) and Field Programmable Gate Arrays (FPGAs) are becoming a critical part of every system design.  There are many different FPGAs with different architectures/ processes. There are four main categories of FPGAs currently commercially available: symmetrical array, row-based, hierarchical PLD and sea-of-gates. In all of these FPGAs the interconnections and how they are programmed vary. Currently there are five technologies in use. They are: static RAM cells, anti-fuse, EPROM transistors, EEPROM transistors and FLASHROM based FPGAs. Depending upon the application, one FPGA technology may have features desirable for that application:


  • Static RAM technology: In the static RAM FPGA programmable connections are made using pass-transistors, transmission gates, or multiplexers that are controlled by SRAM cells. This technology allows fast in-circuit reconfiguration. The major disadvantage is the size of the chip required by the RAM technology and that the chip configuration needs to be loaded to the chip from external source (usually non-volatile memory chip). The FPGA can either actively read its configuration data out of external serial or byte-parallell PROM (master mode), or the configuration data can be written into the FPGA (slave and peripheral mode). The FPGA can be programmed an unlimited number of times. This type of FPGA suffer from reliability problems associated with neutron-induced configuration errors. These so called 'firm errors', while more prevalent at higher altitudes, are still a significant problem at 'commercial' altitudes, this is because form errors can cause an SRAM FPGA's design to change unexpectedly, possibly leading to a system malfunction. Firm errors are the predominant failure mechanism in SRAM-based FPGAs at all altitudes, and they have a failure rate up to two orders the magnitude higher than industry norms at commercial altitudes. In high-volume applications, such as thise found in automotive and consumer electronics market, ensuring product quality and reliability are key criteria for achieving market success and issues that must be addressed by the value FPGA product offerings.
  • Anti-Fuse technology: An anti-fuse resideds in a high-impedance state; and can be programmed into low-impedance or "fused" state. This technology can be used to program devices that are less expensive than the RAM technology.
  • EPROM technology: This method is the same as used in the EPROM memories. The programming is stored without external storage of configuration. EPROM based programmable chips cannot be re-programmed in-circuit and need to be cleared with UV erasing.
  • EEPROM technology: This method is the same as used in the EEPROM memories. The programming is stored without external storage of configuration. EEPROM based programmable chips can be electrically erased but generally cannot be re-programmed in-circuit.
  • FLASHROM based: as with ASICs, the nonvolatile nature of reporgrammable Flash-based devices provides the key advantage of this technology over volatile SRAM-based offerings. Most of the Flash based FPGAs (for instance ProASIC3 from Actel) use a Flash programming cell to control the gate of the switch within the FPGA fabric. Each switch has a single sense gate (the switch) and a single Flash floating gate that controls the state of the switch. In contrast, SRAM-based FPGAs rely on a six-transistor SRAM element for switch control and a pass gate for the switch itself. Unlike Flash-based devices, the volatile SRAM FPGA programming element must be loaded from an external device at every system power-up. This difference means that Flash-based FPGAs are single-chip and live at power-up, which can translate into significant board-level cost savings (smaller PCB's). From a system security standpoint, Flash-based FPGAs are the only FPGA technology that is secure, immune from firm errors, and supports secure remote updates over public networks. This higher level of security offers better protection against theft of critical IP. The devices' firm error immunity reduces the CEM's risk of product liability and increases the system reliability. The capability to conduct secure remote updates enable the product developer to ypdate the product after deployment and, in the process, support a subscription-based business model througn remote updates for feature enhancement. The inclusion of a small, nonvolatile memory (NVM) in Flash devices can serve as an enabling technology in many consumer and automotive applications. The NVM can be used to store encryption keys for secure communications or to support device serialization in set-top boxes for boardcast-based systems.

Many emerging applications in communication, computing and consumer elecronics industries demand that their functionality stays flexible after the system has been manufactured. Such flexibility is required in order to cope with changing user requirements, improvements in systems features, chaning protocol and data-coding standards, demands to support variety of different user applications, etc. An FPGA has a large number of these cells available to use as building blocks in complex digital circuits. Custom hardware has never been so easy to develop. Like microprocessors, RAM based FPGAs can be infinitely reprogrammed in-circuit in only a fraction of a second. Design revisions, even for a fielded product, can be implemented quickly and painlessly. Taking advantage of reconfigurable system design is still very limited. Many such existing tools are based on conventional static FPGA design flows, and demand expert skills and improvisation in  order to produce a working reconfigurable system. Theoretically, FPGAs combine the speed of dedicated, application-optimized hardware with the ability to flexibly change chip resource allocation, so the same system can run manu applications, optimized for each one. But FPGAs have historically been so hard to program that it's been very hard an expensive to use these advantages.  Untill today....

One of the most important applications of FPGA's today is a softcore microprocessor that is coded into a FPGA.

There are new opportunities for FPGAs in the future because there is the fact that the FPGA unit costs are decreasing (FPGA vendors are able to offer programmable devices at unit costs comparable to traditional ASICs). The other thing where you see that the FPGA will make in in the future is that the ASIC NREs are much to high. It is common to see mask costs for ASIC design that is in the millions of dollars.