Patents
Granted Patents
- US Patent 7016304: Link level retry scheme
Ching-Tsun Chou, Suresh Chittor, Andalib Khan, Akhilesh Kumar, Phanindra K Mannava, Rajee S Ram, Sujoy Sen, Srinand Venkatesan, Kiran Padwekar.
- US Patent 8099558: Fairness mechanism for starvation prevention in directory-based cache coherence protocols
Akhilesh Kumar Seungjoon Park, Ching-Tsun Chou.
- US Patent 8205045: Satisfying memory ordering requirements between partial writes and non-snoop accesses
Robert H Beers, Ching-Tsun Chou, Robert J Safranek.
- US Patent 8250311 & 9703712: Satisfying memory ordering requirements between partial reads and non-snoop accesses
Robert H Beers, Ching-Tsun Chou, Robert J Safranek, James Vash.
- US Patent US8443337: Methodology and tools for table-based protocol specification and model generation
Ching-Tsun Chou, Phanindra K Mannava, Seungjoon Park.
- US Patent US8693319: Scheme for avoiding deadlock in multi-ring interconnect, with additional application to congestion control
Ching-Tsun Chou, Naveen Cherukuri.
Pending Patent Applications
- US Patent Application 11965158: Interconnect architectural state coverage measurement methodology
Phanindra Mannava, Seungjoon Park, Ajit Dingankar, Ching-Tsun Chou, Nikhil Mittal, Radhakrishnan V Mahalikudi, Mayank Singhal.
- US Patent Application 12061027: Adaptive cache organization for chip multiprocessors
Naveen Cherukuri, Ioannis Schoinas, Akhilesh Kumar, Seungjoon Park, Ching-Tsun Chou.