Profile

Samson Sheng-Hsiung Chen Ph. D.

E-mail: chenss65 (at) gmail.com

Education:

  • B.S. in Computer Science and Information Engineering, National Chiao Tung University (1998)

  • Ph.D. in Computer Science, National Chiao Tung University (2008)

Background:

Research Interests:

Design Technology Co-Optimization, Electronic Design Automation (EDA), Distributed Algorithms

Awards:

  • Nov. 1995: Academic Achievement Award

  • Nov. 1997: Academic Achievement Award

  • May 1999: Academic Achievement Award

  • Nov. 1999: Academic Achievement Award

  • Jun. 2006: Research Poster Award (CSIE, NCTU)

  • Apr. 2012: Hsinchu Science Park 2012 Outstanding Employee Award

Publications:

Journal Papers

  1. Fong-Yuan Chang, Ren-Song Tsay, Wai-Kei Mak and Sheng-Hsiung Chen, MANA: A Shortest Path MAze Algorithm under Separation and Minimum Length NAnometer Rules, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. Volume: 32, Issue: 10, Oct. 2013, pp. 1557-1568.

  2. Sheng-Hsiung Chen and Ting-Lu Huang, Bounded-Bypass Mutual Exclusion with Minimum Number of Registers, IEEE Transaction on Parallel and Distributed Systems. Volume: 20, Issue: 12, Dec. 2009, pp. 1726-1737. (SCI and EI)

  3. Sheng-Hsiung Chen and Ting-Lu Huang, A Tight Bound on Remote Reference Time Complexity of Mutual Exclusion in the Read-Modify-Write Model, Journal of Parallel and Distributed Computing. Volume: 66, Issue: 11, Nov. 2006, pp. 1455-1471. (SCI and EI)

Conference Papers

  1. Fong-Yuan Chang, Ren-Song Tsay, Wai-Kei Mak and Sheng-Hsiung Chen, A Separation and Minimum Wire Length Constrained Maze Routing Algorithm Under Nanometer Wiring Rules, in ASP-DAC 2013, pp. 175-180.

  2. Fong-Yuan Chang, Sheng-Hsiung Chen, Ren-Song Tsay and Wai-Kei Mak, Cut-Demand Based Routing Resource Allocation and Consolidation for Routability, in ASP-DAC 2011, pp. 533-538.

  3. Sheng-Hsiung Chen and Ting-Lu Huang, A Fair and Sapce-Efficient Mutual Exclusion, in Proceedings of the 11th International Conference on Parallel and Distributed Systems (ICPADS 2005), IEEE, pp. 467-473, Fukuoka, Japan, July 2005. [Talk Slides]

  4. Sheng-Hsiung Chen and Ting-Lu Huang, A Tight Bound on Time Complexity of Mutual Exclusion, in Proceedings of the International Computer, pp. 1352-1357, Taipei, Taiwan, Dec. 2004. [Full Version] [Talk Slides]

  5. Sheng-Hsiung Chen and Ting-Lu Huang, A Fair and Space-Efficient Mutual Exclusion Using Read/Write and fetch&store Primitives, in Proceedings of the International Conference on Informatics, Cybernetics, and Systems (ICICS'03), pp. 1059-1064, Kaohsiung, Taiwan, Dec. 2003. [Talk Slides]

US Patents

Pending

  1. Sheng-Hsiung Chen, Jerry Chang-Jui Kao, Fong-Yuan Chang, Po-Hsiang Huang, Shao-Huan Wang, XinYong Wang, Yi-Kan Cheng, Chun-Chen Chen, "Standard Cells and Variations thereof within a Standard Cell Library." (Publication number: 20200328202)

  2. Sheng-Hsiung Chen, Chung-Te Lin, Fong-Yuan Chang, Ho Che Yu, Li-Chun Tien, "Integrated Circuit and Layout Method for Standard Cell Structures." (Publication number: 20200327274)

  3. Chi-Lin Liu, Sheng-Hsiung Chen, Jerry Chang-Jui Kao, Fong-Yuan Chang, Lee-Chung Lu, Shang-Chih Hsieh, Wei-Hsiang Ma, "Method and System of Expanding Set of Standard Cells which Comprise a Library." (Publication number: 20200272778)

  4. Sheng-Hsiung Chen, Jyun-Hao Chang, Ting-Wei Chiang Fong-Yuan Chang, I-Lun Tseng, Po-Hsiang Huang, "Method of Modifying Cell, System for Modifying Cell and Global Connection Routing Method ." (Publication number: 20200167518 )

  5. Fong-Yuan Chang, Sheng-Hsiung Chen, Ting-Wei Chiang, Chung-Te Lin, Jung-Chan Yang Lee-Chung Lu, Po-Hsiang Huang, Chun-Chen Chen, "Pin Modification for Standard Cells." (Publication number: 20200152617)

  6. Pin-Dai Sue, Chin-Chou Liu, Sheng-Hsiung Chen, Fong-Yuan Chang, Lee-Chung Lu, Yen-Hung Lin, Li-Chun Tien, Po-Hsiang Huang, Yi-Kan Cheng Chi-Yu Lu, "Integrated Circuit FIN Layout Method System, and Structure" (Publication number: 20200134124)

  7. Po-Hsiang Huang, Chin-Chou Liu, Sheng-Hsiung Chen, Fong-Yuan Chang Hui-Zhong Zhuang, Meng-Hsueh Wang, Yi-Kan Cheng, Chun-Chen Chen, "Semiconductor Device with Filler Cell Region, Method of Generation Layout Diagram and System for Same." (Publication number: 20200134125)

  8. Fong-Yuan Chang, Kuo-Nan Yang, Chung-Hsing Wang, Lee-Chung Lu, Sheng-Fong Chen, Po-Hsiang Huang, Hiranmay Biswas, Sheng-Hsiung Chen, Aftab Alam Khan, "Integrated Circuit and Method of Generation Integrated Circuit Layout ." (Publication number: 20200126967)

  9. Sheng-Hsiung Chen, Fong-Yuan Chang Ho Che Yu, "Semiconductor Device with Cell Region, Method of Generating Layout Diagram and System for same ." (Publication number: 20200104462)

  10. Sheng-Hsiung Chen, Shao-Huan Wang, Wen-Hao Chen, Chun-Yao Ku, Hung-Chih Ou, "Integrated Circuit and Method of Forming Same and a System ." (Publication number: 20200097634)

  11. Shao-Huan Wang, Sheng-Hsiung Chen, Fong-Yuan Chang, Po-Hsiang Huang, "Placement Constraint Method for Multiple Patterning of Cell-Based Chip Design." (Publication number: 20200089840)

  12. Fong-Yuan Chang, Chin-Chou Liu, Sheng-Hsiung Chen, Po-Hsiang Huang, "Method for Generating Layout Diagram Including Protruding Pin Cell Regions and Semiconductor Device Based on Same." (Publication number: 20200019670)

  13. Fong-Yuan Chang, Kuo-Nan Yang, Chung-Hsing Wang, Lee-Chung Lu, Sheng-Fong Chen, Po-Hsiang Huang, Hiranmay Biswas, Sheng-Hsiung Chen, Aftab Alam Khan, "Integrated Circuit and Method of Generating Integrated Circuit Layout." (Publication number: 20190148352)

  14. Fong-Yuan Chang, Jyun-Hao Chang, Sheng-Hsiung Chen, Po-Hsiang Huang, Lipen Yuan, "Integrated Circuit, System for and Method of Forming an Integrated Circuit ." (Publication number: 20190096872)

  15. Fong-yuan Chang, Chun-Chen Chen, Po-Hsiang Huang, Lee-Chung Lu, Chung-Te Lin, Jerry Chang Jui Kao, Sheng-Hsiung Chen, Chin-Chou Liu, "Integrated Circuit Device with Improved Layout." (Publication number: 20190035811)

  16. Fong-Yuan Chang, Jyun-Hao Chang, Sheng-Hsiung Chen, Ho Che Yu, Lee-Chung Lu, Ni-Wan Fan, Po-Hsiang Huang, Chi-Yu Lu, Jeo-Yen Lee, "Cell Structures and Semiconductor Devices Having Same." (Publication number: 20180150592)

Grant

  1. US Patent 10817643, Shao-Huan Wang, Sheng-Hsiung Chen, Wen-Hao Chen, Chun-Chen Chen, Hung-Chih Ou, "Method of Designing Semiconductor Device and System for Implementing the Method." (2020)

  2. US Patent 10804200, Sheng-Hsiung Chen, Chung-Hsing Wang, Fong-yuan Chang, Lee-Chung Lu, Li-Chun Tien, Po-Hsiang Huang, Shao-huan Wang, Ting Yu Chen, Yen-Pin Chen, Chun-Chen Chen, Tzu-Hen Lin, Tai-Yu Cheng, "Integrated Circuit Having a High Cell Density ." (2020)

  3. US Patent 10797041, Fong-Yuan Chang, Jyun-Hao Chang, Sheng-Hsiung Chen, Po-Hsiang Huang, Lipen Yuan, "Integrated Circuit, System for and Method of Forming an Integrated Circuit." (2020)

  4. US Patent 10776557, Po-Hsiang Huang, Sheng-Hsiung Chen, Fong-Yuan Chang, "Integrated Circuit Structure." (2020)

  5. US Patent 10777505, Fong-Yuan Chang, Sheng-Hsiung Chen, Po-Hsiang Huang, Jyun-Hao Chang, Chun-Chen Chen, "Method of Fabrication Integrated Circuit Having Staggered Conductive Features." (2020)

  6. US Patent 10776551, Meng-Kai Hsu, Sheng-Hsiung Chen, Wai-Kei Mak, Ting-Chi Wang, Yu-Hsiang Cheng, Ding-Wei Huang, "Method and System of Revising a Layout Diagram." (2020)

  7. US Patent 10741539, Sheng-Hsiung Chen, Jerry Chang-Jui Kao, Fong-Yuan Chang, Po-Hsiang Huang, Shao-Huan Wang, XinYong Wang, Yi-Kan Cheng, Chun-Chen Chen, "Standard Cells and Variations thereof within a Standard Cell Library ." (2020)

  8. US Patent 10733352, Sheng-Hsiung Chen, Chung-Te Lin, Fong-Yuan Chang, Ho Che Yu, Li-Chun Tien, "Integrated Circuit and Layout Method for Standard Cell Structures ." (2020)

  9. US Patent 10678987, Sheng-Hsiung Chen, Fong-Yuan Chang , "Cell Layout Method and System for Creating Stacked 3D Integrated Circuit Having Two Tiers ." (2020)

  10. US Patent 10559558, Fong-yuan Chang, Sheng-Hsiung Chen, Ting-Wei Chiang, Chung-Te Lin, Jung-Chan Yang, Lee-Chung Lu, Po-Hsiang Huang, Chun-Chen Chen , "Pin Modification for Standard Cells ." (2020)

  11. US Patent 10552568, Sheng-Hsiung Chen, Jyun-Hao Chang, Ting-Wei Chiang, Fong-Yuan Chang, I-Lun Tseng, Po-Hsiang Huang , "Method of Modifying Cell and Global Connection Routing Method." (2020)

  12. US Patent 10521545, Shao-Huan Wang, Sheng-Hsiung Chen, Fong-Yuan Chang, Po-Hsiang Huang , "Placement Constraint Method for Multiple Patterning of Cell-based Chip Design." (2019)

  13. US Patent 10515944, Fong-Yuan Chang, Kuo-Nan Yang, Chung-Hsing Wang, Lee-Chung Lu, Sheng-Fong Chen, Po-Hsiang Huang, Hiranmay Biswas, Sheng-Hsiung Chen, Aftab Alam Khan, "Integrated Circuit and Method of Generating Integrated Circuit Layout ." (2019)

  14. US Patent 10509887, Sheng-Hsiung Chen, Ming-Huei Tsai, Shao-Huan Wang, Shu-Yu Chen, Wen-Hao Chen, Chun-Chen Chen, "Must-join Pin Sign-off Method." (2019)

  15. US Patent 10402534, Po-Hsiang Huang, Sheng-Hsiung Chen, Fong-Yuan Chang, "Integrated Circuit Layout Methods, Structures, and Systems." (2019)

  16. US Patent 10396063, Fong-Yuan Chang, Lee-Chung Lu, Yi-Kan Cheng, Sheng-Hsiung Chen, Po-Hsiang Huang, Shun Li Chen, Jeo-Yen Lee, Jyun-Hao Chang, Shao-Huan Wang, Chien-Ying Chen, "Circuit with Combined cells and Method for Manufacturing the Same ." (2019)

  17. US Patent 10312192, Fong-Yuan Chang, Sheng-Hsiung Chen, Po-Hsiang Huang, Jyun-Hao Chang, Chun-Chen Chen, "Integrated Circuit Having Staggered Conductive Features." (2019)

  18. US Patent 10289794 , Shao-Huan Wang, Sheng-Hsiung Chen, Wen-Hao Chen, Chun-Chen Chen, Hung-Chih Ou, "Layout for Semiconductor Device Including Via Pillar Structure." (2019)

  19. US Patent 10262981, Fong-Yuan Chang, Jyun-Hao Chang, Sheng-Hsiung Chen, Po-Hsiang Huang, Lipen Yuan ,"Integrated Circuit, System for and Method of Forming an Integrated Circuit " (2019)

  20. US Patent 10192019, Fong-Yuan Chang, Sheng-Hsiung Chen, Ren-Song Tsay and Wai-Kei Mak, "Separation and Minimum Wire Length Constrained Maze Routing Method and System." (2019)

  21. US Patent 10157251, Hung-Chih Ou, Chun-Chen Chen, Sheng-Hsiung Chen, "Method and System for Partitioning Circuit Cells." (2018)

  22. US Patent 10157840, Sheng-Hsiung Chen, Chung-Hsing Wang, Fong-yuan Chang, Lee-Chung Lu, Li-Chun Tien, Po-Hsiang Huang, Shao-huan Wang, Ting Yu Chen, Yen-Pin Chen, Chun-Chen Chen, Tzu-Hen Lin, Tai-Yu Cheng, "Integrated Circuit Having a High Cell Density." (2018)

  23. US Patent 10128234, Ni-Wan Fan, Sheng-Hsiung Chen, Cheng-I Huang, Jung-Chan Yang, Hsiang-Jen Tseng, Chi-Yu Lu, "Electromigration Resistant Semiconductor Device." (2018)

  24. US Patent 9996657, Chun-Chen Chen, Sheng-Hsiung Chen, Fong-Yuan Chang, Shao-Huan Wang, "Systems and Methods for Generating a Multiple Patterning Lithography Compliant Integrated Circuit Layout." (2018)

  25. US Patent 9846759, Sheng-Hsiung Chen, Jyun-Hao Chang, Ting-Wei Chiang, Fong-Yuan Chang, I-Lun Tseng, Po-Hsiang Huang, "Global Connection Routing Method and System for Performing the Same." (2017)

  26. US Patent 9665679, Fong-Yuan Chang, Sheng-Hsiung Chen, Tung-Chieh Chen, Ren-Song Tsay, Wai-Kei Mak, "Systems and Methods for Designing Integrated Circuits with Consideration of Horizontal and Vertical Wiring Demand Ratios." (2017)

  27. US Patent 8832632 , Fong-Yuan Chang and Sheng-Hsiung Chen, "Compact Routing." (2014)

  28. US Patent 8782588, Fong-Yuan Chang, Wei-Shun Chuang, Sheng-Hsiung Chen, Hsian-Ho Chang, Ruey-Shi Rau, "Multiple Level Spine Routing." (2014)

  29. US Patent 8683417, Fong-Yuan Chang, Wei-Shun Chuang, Sheng-Hsiung Chen, Hsian-Ho Chang, Ruey-Shi Rau, "Multiple Level Spine Routing." (2014)

  30. US Patent 8407647, Fong-Yuan Chang, Sheng-Hsiung Chen, Tung-Chieh Chen, Ren-Song Tsay, Wai-Kei Mak, "Systems and Methods for Designing and Making Integrated Circuits with Consideration of Wiring Demand Ratio." (2013)

Ph.D. Dissertation

Tight Bounds on Space and Remote Memory Reference Time Complexity of Mutual Exclusion

Advisor: Prof. Ting-Lu Huang

[Dissertation] [Slides for the defense on 14 Feb. 2008]

This page was last modified on Nov. 3, 2020.