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There are tons of references on Verilog out there. If you find one you love, share it on Piazza and we'll add it to this list.

One caveat: many references will use older styles of e.g. module definition and port declaration. Just be aware there there is more than one way to do things due to the language's history, but in this class we'll prefer the clearer, more explicit modern forms.


Test benches


  • Verilog Preprocessor: Force for `Good and `Evil - Slides (pdf), Paper (pdf)