Byungchul Hong

Contacts

  • byungchul.hong@gmail.com

  • Curriculum Vitae [pdf]


Research Interests

  • Scalable Near-data Processing Architecture

  • Deep learning Acceleration, Interconnection Network


Work Experience

  • Samsung Electronics (Dec. 2020 ~ Present)

    • Principle Engineer

    • Exynos NPU development -- Next gen. architecture, Performance/power modeling, u-Arch.

  • FuriosaAI (Oct. 2018 ~ Nov. 2020)

    • Principle NPU Architect

    • High-performance neural processing unit (NPU) architecture and logic design

  • Arteris (Apr. 2011 ~ Sep. 2018)

    • Senior Solutions Architect

    • Network-on-chip, Cache-coherent interconnect IP

  • SystemIC R&D Lab. LG Electronics (Feb. 2008 ~ Apr. 2011)

    • Research Engineer, SoC Platform team

    • CPU sub-system, Interconnect architecture design for High-performance SoCs.


Education

  • Ph.D (Mar. 2013 ~ Aug. 2018)

    • KAIST

    • Computer Science (Advisor : Prof. John Kim)

    • Thesis : Near-data Processing on Memory-centric Network Architecture for Data-intensive Workloads [paper][slide]

  • M.S (Feb. 2006 ~ Feb. 2008)

    • KAIST

    • Electrical Engineering (Advisor : Prof. Jongmin Kyung)

    • Thesis : Real-time Trace for Performance Analysis in Embedded Processors

  • B.S (Mar. 2002 ~ Feb. 2006)

    • KAIST

    • Electrical Engineering


Publications

  • Multi-dimensional Parallel Training of Winograd Layer on Memory-Centric Architecture [paper][slide]

    • The 51st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), 2018

    • Byungchul Hong, Yeonju Ro, and John Kim

  • Accelerating Linked-list Traversal Through Near-Data Processing [paper][slide]

    • The 25th International Conference on Parallel Architectures and Compilation Techniques (PACT), 2016

    • Byungchul Hong, Gwangsun Kim, Jung Ho Ahn, Yongkee Kwon, Hongsik Kim, and John Kim

  • Adaptive and Flexible Key-Value Stores Through Soft Data Partitioning [paper][slide]

    • The 34th IEEE International Conference on Computer Design (ICCD), 2016

    • Byungchul Hong, Yongkee Kwon, Jung Ho Anh, and John Kim

  • Emulation Based High-Accuracy Throughput Estimation for High-Speed Connectivities : Case Study of USB2.0 [paper][slide]

    • The 48th Design Automation Conference (DAC), 2011

    • Byungchul Hong, Chulho Shin, and Daehyup Ko

  • A two-phased multimedia SoC design optimization using ESL tools [slide]

    • The 47th Design Automation Conference (DAC) User Track, 2010

    • Hoon Oh, Youngkil Park, Byungchul Hong, Chulho Shin and Derek Ko


Honors and Awards

  • Best paper finalist

    • International Conference on Parallel Architectures and Compilation Techniques (PACT), 2016

    • Authors: Byungchul Hong, Gwangsun Kim, Jung Ho Ahn, Yongkee Kwon, Hongsik Kim, John Kim

  • Ministry of Commerce and Industry Award

    • 1st place in SoC Design Contest, Ministry of Commerce and Industry

    • Title: Real-time Trace for Performance Analysis in OR1200

    • Project leader