Benoît Dupont de Dinechin

Professional Page

Contact

benoit.dinechin@gmail.com

Education

  • Engineer from the École Nationale Supérieure de l'aéronautique et de l'Espace (ENSAE), Toulouse, France in 1985.
  • Master of Science in Computer Systems from the Université Paul Sabatier, Toulouse, France, in 1986.
  • PhD in Computer Science from the Université de Paris 6, laboratoire MASI, Paris, France, in 1991.
  • Invited scientist at the McGill University, School of Computer Science, Montréal, Canada, in 1995 and 1996.

Career Outline

  • Commissariat a l'Energie Atomique, Direction des Applications Militaires, France, from 1989 to mid 1998.
  • Part-time consultant at Cray Research Inc., Minnesota, USA, from 1992 to 1997.
  • Software engineer at STMicroelectronics Grenoble, France, from mid-1998 to mid-2004.
  • Research engineer at STMicroelectronics Manno, Switzerland, from mid-2004 to mid-2007.
  • Research and Development responsible at STMicroelectronics Grenoble, France, from mid-2007 to early 2009.
  • STMicroelectronics National Fellow in November 2008.
  • Compiler team leader and company fellow at Kalray in February 2009.
  • Director of software development at Kalray in February 2012.
  • Chief Technology Officer at Kalray since March 2013.

Contributions

  • Designed and developed the software pipeliner for the Cray T3E production compilers.
  • Contributed to the design of Cray F--, the first PGAS language and the ancestor of Co-Array Fortran.
  • Led the development of the linear assembly optimizer (LAO) for the STMicroelectronics ST120 VLIW-DSP core.
  • Led the development of the production compiler for the STMicroelectronics ST200 VLIW family based on the Open64 and a SSA-based code generator.
  • Designed and developed the Machine Description System (MDS) used by STMicroelectronics production compilation tools.
  • Initiated the STMicroelectronics Manno project that established the applicability of CLI program representation (.NET byte code) to C media processing using JIT compilation on VLIW cores.
  • Architected the Kalray VLIW core and co-architected the Kalray 1st-generation massively parallel processing array (MPPA) processors.
  • Led the development of software tools and run-time libraries of the 1st-generation MPPA processor, in the areas of cyclostatic dataflow and explicit parallel programming models.
  • Advanced the architecture and programming models of the 2nd-generation MPPA processor for the support of time-critical applications.
  • Designed the NoC + DDR guaranteed services framework of the 2nd-generation MPPA processor based on deterministic network calculus.
  • Designed the security architecture of the 3rd-generation MPPA processor to meet defense, avionics and automotive security requirements.

Bibliography

Books and Journals

  • Georgia Giannopoulou, Nikolay Stoimenov, Pengcheng Huang, Lothar Thiele, Benoît Dupont de Dinechin "Mixed-criticality scheduling on cluster-based manycores with shared communication and storage resources", Real-Time Systems vol. 51, pp. 1-51 (May 2015).
  • Benoît Dupont de Dinechin, Alix Munier‑Kordon "Converging to Periodic Schedules for Cyclic Scheduling Problems with Resources and Deadlines", Computers & Operations Research, vol. 51, pp. 227-236 (2014).
  • Alix Munier‑Kordon, Fadi Kacem, Benoît Dupont de Dinechin, Lucian Finta "Scheduling an interval ordered precedence graph with communication delays and a limited number of processors", RAIRO-Oper. Res. 47 (2013) 73–87.
  • Dibyendu Das, Benoît Dupont de Dinechin, Ramakrishna Upadrasta "Efficient liveness computation using merge sets and DJ-graphs" TACO 8(4): 27 (2012).
  • Sid Ahmed Ali Touati, Frédéric Brault, Karine Deschinkel, Benoît Dupont de Dinechin "Efficient Spilling Reduction for Software Pipelined Loops in Presence of Multiple Register Types" ACM Trans. Embedded Comput. Syst. 10(4): 47 (2011).
  • Benoit Dupont-de-Dinechin, Christian Artigues, Sadia Azem "Resource-Constrained Modulo Scheduling" Resource-Constrained Project Scheduling: Models, Algorithms, Extensions and Applications, January 2008.
  • Benoît Dupont de Dinechin "From Machine Scheduling to VLIW Instruction Scheduling" ST Journal of Research Volume 1, Number 2, September 2004.
  • Benoît Dupont de Dinechin, Christophe Monat, Patrick Blouet, Christian Bertin "DSP-MCU Processor Optimization for Portable Applications" Microelectronic Engineering Volume 54 Issue 1, December 2000.

Conference Papers

  • Benoît Dupont de Dinechin, Amaury Graillat "Network-on-Chip Service Guarantees on the Kalray MPPA-256 Bostan Processor" AISTECS: 2nd International Workshop on Advanced Interconnect Solutions and Technologies for Emerging Computing Systems, HiPEAC 2017 Stockholm Conference, January 2017.
  • Bruno Bodin, Alix Munier Kordon, Benoît Dupont de Dinechin "Optimal and Fast Throughput Evaluation of CSDF" Proceedings of the 53rd Annual Design Automation Conference DAC '16, June 5-9 2016, Austin, Texas, USA (HiPEAC Paper Award).
  • Selma Saidi, Rolf Ernst, Sascha Uhrig, Henrik Theiling, Benoît Dupont de Dinechin "The Shift to Multicores in Real-Time and Safety-Critical Systems" CODES+ISSS 2015 invited paper, October 4–9 2015, Amsterdam, The Netherlands.
  • Julien Hascoet, Andrew Ensor, Jean-François Nezan, Benoît Dupont De Dinechin "Implementation of a Fast Fourier Transform onto a Manycore Embedded System" DASIP 2015, September 2325 2015, Cracow, Poland.
  • Benoît Dupont de Dinechin, Yves Durand, Duco van Amstel, Alexandre Ghiti "Guaranteed Services of the NoC of a Manycore Processor" NoCArc 2014, December 13rd 2014, Cambridge, U.K.
  • Benoît Dupont de Dinechin “Using the SSA-Form in a Code Generator" CC 2014 invited paper, LNCS 8409, pp. 1–17, 2014.
  • Benoît Dupont de Dinechin, Duco van Amstel, Marc Poulhiès, Guillaume Lager  “Time-Critical Computing on a Single-Chip Massively Parallel Processor" DATE 2014 invited paper for special session SD1 “Predictable Multi-Core Computing", 24-28 March 2014, Dresden, Germany.
  • Bruno Bodin, Alix Munier‑Kordon, Benoît Dupont de Dinechin “Periodic Schedules for Cyclo-Static Dataflow" ESTIMedia 2013: Symposium on Embedded Systems for Real-Time Multimedia, Embedded Systems Week, September 29 – October 4, 2013, Montreal.
  • Benoît Dupont de Dinechin, Renaud Ayrignac, Pierre-Edouard Beaucamps, Patrice Couvert, Francois Jacquet, Samuel Jones, Nicolas Morey Chaisemartin, Frederic Riss, Thierry Strudel "A Clustered Manycore Processor Architecture for Embedded and Accelerated Applications" IEEE HPEC'13, September 2013, Waltham, MA USA.
  • Benoît Dupont de Dinechin, Pierre Guironnet de Massas, Guillaume Lager, Clément Léger, Benjamin Orgogozo, Jérôme Reybert and Thierry Strudel "A Distributed Run-Time Environment for the Kalray MPPA-256 Integrated Manycore Processor", ICCS 2013 ALCHEMY Workshop, June 2013.
  • Pascal Aubry, Pierre-Edouard Beaucamps, Frédéric Blanc, Bruno Bodin, Sergiu Carpov, Loïc Cudennec, Vincent David, Philippe Dore, Paul Dubrulle, Benoît Dupont de Dinechin, François Galea, Thierry Goubier, Michel Harrand, Samuel Jones, Jean-Denis Lesage, Stéphane Louise, Nicolas Morey Chaisemartin, Thanh Hai Nguyen, Xavier Raynaud and Renaud Sirdey "Extended Cyclostatic Dataflow Program Compilation and Execution for an Integrated Manycore Processor", ICCS 2013 ALCHEMY Workshop, June 2013.
  • Benoît Dupont de Dinechin, Julien Villette, Ayrignac Renaud, Vincent Ray et Nicolas Brunie "Conception et mise en œuvre d’une architecture VLIW pour le calcul embarqué", ComPAS'13, January 2013.
  • Nicolas Brunie, Florent De Dinechin et Benoît De Dinechin "Conception d’une matrice reconfigurable pour coprocesseur fortement couplé", ComPAS'13, January 2013.
  • Bruno Bodin, Alix Munier‑Kordon, Benoît Dupont de Dinechin “K-Periodic Schedules for Evaluating the Maximum Throughput of a Synchronous Dataflow Graph”, SAMOS Inter. Conf. on Embedded Computer Systems, vol. 12, 2012.
  • Nicolas Brunie, Florent de Dinechin, and Benoît Dupont de Dinechin "A mixed-precision fused multiply and add" 45th Asilomar Conference on Signals, Systems & Computers, 2011.
  • Benoit Boissinot, Florian Brandner, Alain Darte, Benoît Dupont de Dinechin, Fabrice Rastello "A Non-iterative Data-Flow Algorithm for Computing Liveness Sets in Strict SSA Programs" Programming Languages and Systems - 9th Asian Symposium APLAS 2011.
  • Frédéric Brault, Benoît Dupont de Dinechin, Sid Ahmed Ali Touati, Albert Cohen "Software Pipelining and Register Pressure in VLIW Architectures" ODES 2010.
  • Benoit Boissinot, Alain Darte, Fabrice Rastello, Benoît Dupont de Dinechin, Christophe Guillon "Revisiting Out-of-SSA Translation for Correctness, Code Quality, and Efficiency (Best Paper)" CGO 2009.
  • Benoît Dupont de Dinechin "Inter-Block Scoreboard Scheduling in a JIT Compiler for VLIW Processors" Euro-Par 2008 (with slides).
  • Benoit Boissinot, Sebastian Hack, Daniel Grund, Benoît Dupont de Dinechin, Fabrice Rastello "Fast Liveness Checking for SSA-Form Programs (Best Paper)" CGO 2008 (with slides).
  • Benoît Dupont de Dinechin "Scheduling Monotone Interval Orders on Typed Task Systems" PlanSIG 2007 (with slides).
  • Benoît Dupont de Dinechin "Time-Indexed Formulations and a Large Neighborhood Search for the Resource-Constrained Modulo Scheduling Problem" MISTA 2007 (with slides).
  • Sadia Azem, Benoit Dupont-de-Dinechin, Christian Artigues "Résolution d'un problème d'ordonnancement modulo sur une architecture VLIW par la programmation linéaire en nombre entiers" ROADEF 2006 (with slides).
  • Florent Blachot, Benoît Dupont de Dinechin, Guillaume Huard "SCAN: a Heuristic for Near-Optimal Software Pipelining" Euro-Par 2006.
  • Jean-Michel Muller, Arnaud Tisserand, Benoît Dupont de Dinechin, Christophe Monat "Division by Constant for the ST100 DSP Microprocessor" ARITH 2005.
  • Christian Bertin, Nicolas Brisebarre, Benoît Dupont de Dinechin, C.-P. Jeannerod, C. Monat, J.-M. Muller, S.K. Raina and A. Tisserand "A Floating-Point Library for Integer Processors" SPIE 2004.
  • Benoît Dupont de Dinechin "Modulo Scheduling with Regular Unwinding" DOM 2004 (with slides).
  • Benoît Dupont de Dinechin, Christophe Monat, Fabrice Rastello "Parallel Execution of the Saturated Reductions" SIPS 2001.
  • Benoît Dupont de Dinechin, François de Ferrière, Christophe Guillon, Artour Stoutchinin "Code Generator Optimizations for the ST120 DSP-MCU Core" CASES 2000.
  • Benoît Dupont de Dinechin "Extending Modulo Scheduling with Memory Reference Merging" CC 1999.
  • Benoît Dupont de Dinechin "A Unified Software Pipeline Construction Scheme for Modulo Scheduled Loops" PaCT 1997.
  • Robert W. Numrich, Jon L. Steidel, Brian H. Johnson, Benoît Dupont de Dinechin, Gary Elsesser, Greg Fischer, Tom MacDonald "Definition of the F-- Extension to Fortran 90" LCPC 1997.
  • Benoît Dupont de Dinechin "Parametric Computation of Margins and of Minimum Cumulative Register Lifetime Dates" LCPC 1996.
  • Benoît Dupont de Dinechin "Insertion Scheduling: An Alternative to List Scheduling for Modulo Schedulers" LCPC 1995.
  • Benoît Dupont de Dinechin "An Introduction to Simplex Scheduling" PACT 1994.
  • Benoît Dupont de Dinechin "StaCS: a Static Control Superscalar Architecture" MICRO 1992.
  • Benoît Dupont de Dinechin "An Ultra-Fast Euclidean Division Algorithm for Prime Memory Systems" ICS 1991.

Technical Reports

(whenever significantly different from otherwise published work)

Hardware Patents

  • Benoît Dupont de Dinechin, Marta Rybczynska, Vincent Ray "Atomic Instruction Scoped to an Intermediate Cache Level" Filed 2016.
  • Duco van Amstel, Alexandre Blampey, Benoît Dupont de Dinechin "Toket Bucket Flow-Rate Limiter" Filed 2015.
  • Thomas Champseix, Benoît Dupont de Dinechin, Pierre Guironnet de Massas "Hardware Synchronization Barrier Between Processing Units" US2015339173
  • Benoît Dupont de Dinechin, Vincent Ray "Inter-Processor Synchronization System" US2015339256.
  • Renaud Ayrignac,  Vincent Ray, Benoît Dupont de Dinechin "VLIW Type Instruction Packet Structure and Processor Suitable for Processing Such an Instruction Packet" WO2015177427.
  • Benoît Dupont de Dinechin, Marta Rybczynska "Bit Matrix Multiplication Using Explicit Registers" EP2947562, US2015339101.
  • Michel Harrand, Yves Durand, Patrice Couvert, Thomas Champseix, Benoît Dupont de Dinechin "Stream Management in an On-Chip Network" EP2771800, US2014301205.
  • Florent Dupont de Dinechin, Nicolas Brunie, Benoît Dupont de Dinechin "Mixed Precision Fused Multiply Accumulator" EP2702478,  US2014089371.
  • Benoît Dupont de Dinechin "Opérateur saturant à haute efficacité" EU 03354010.
  • Benoît Dupont de Dinechin "Dispositif et procédé d'arbitrage des requêtes et de résolution des conflits lies à l'accès aux mémoires à bancs indépendants" FR 89 00689.

Presentations

Keynote Presentations

  • MCSOC 2016 "Engineering a Manycore Processor Platform for Mission-Critical Applications", September 21st-23rd 2016, Lyon, France.
  • ECRTS16 / RTN'2016 "Guaranteed Services of the NoC and DDR Memory of the MPPA Processor", July 5th-8th 2016, Toulouse, France.
  • EMS 2015 "The MPPA-256 Bostan Manycore Processor for Real-Time and Safety-Critical Systems", November 19th, 2015, Yokohama, Japan.
  • COOL Chips XVIII "The Kalray MPPA Mission-Critical Supercomputer on a Chip" April 13-15, 2015, Yokohama, Japan.
  • CC 2014 (Compiler Construction) "Using the SSA Form in a Code Generator", April 9th 2014, Grenoble, France.
  • DATE 2014 System Level Design session "Time-Critical Computing on a Single Chip Massively Parallel Processor", March 26th 2014, Dresden, Germany.
  • INA-OMC 2014 8th Interconnection Network Architectures: On-Chip, Multi-Chip (INA-OCMC) "Guaranted Services on the Network-on-Chip of the Kalray MPPA Single Chip Manycore Processor" in conjunction with the HiPEAC 2014 conference, January 22nd 2014, Vienna, Austria.
  • MCC 2013 "Architecture and Programming Models of the Kalray MPPA Single Chip Manycore Processor", November 26th 2013, Halmstad, Sweden.
  • DASIP 2013 "Latency-Constrained Image and Signal Processing on a Manycore Processor" October 8th 2013, Cagliari, Italy.
  • MuCoCoS 2013 "Dataflow Language Compilation for a Single Chip Massively Parallel Processor", September 7th, 2013, Edinburgh, Scotland, UK.
  • HiPEAC 2013 "Integrating a distributed memory computer on a chip: challenges and opportunities" January 23rd 2013, Berlin, Germany.
  • ComPAS 2013 "L’interface des réseaux sur puce: une nouvelle frontière architecturale" January 18th 2013, Montbonnot, France.
  • GREPS 2007 "GCC for Embedded VLIW Processors: Why Not?"

Workshop Presentations

  • DATE 2017 W07 "Consolidating High-Performance and High-Integrity Autonomous Driving Functions on the MPPA Manycore Processor", March 31st 2017, Lausanne, Switzerland.
  • DATE 2016 W04 "Model-Based Code Generation for the MPPA Manycore Processor" March 18th 2016, Dresden, Germany.
  • Hot Chips 27 "Revisiting DSP Acceleration with the Kalray MPPA Manycore Processor" August 24th 2015, Cupertino, CA, USA.
  • MPSoC 2013 "Manycore Challenges for the Next Generation of Professional Applications" July 15th 2013, Otsu, Japan.
  • HiPEAC 2013 Spring Computing Week "Network-on-Chip Architecture and Run-Time of the MPPA-256 Manycore Processor" (presented by Duco van Amstel), May 5th 2013, Paris, France.
  • ARCHI'13 "Architectures Manycœurs", March 29th 2013, Col de Porte, France.
  • TORRENTS 2012 "A Distributed Run-Time Environment for an Integrated Manycore Processor" December 12th 2012, Toulouse, France.
  • HiPEAC 2012 Autumn Computing Week "Hybrid Bulk Synchronous Programming on and Integrated Manycore Processor" October 16th 2012, Ghent, Belgium.
  • COMPEEF 2012 "Explicit Parallel Programming Environment on an Integrated Manycore Processor" September 25th 2012, Grenoble WTC, France.
  • HiPEAC 2007 "Inter-Block Scoreboard Scheduling in a JIT Compiler for VLIW processors"
  • MIGAS 2000 "DSP-MCU Processor Optimization for Portable Applications"

Internal Presentations