BALASAHEB  S. DARADE

                                                                                                                                                                  Email: balasaheb@ieee.org

                                                                                                                                                                  Ph: 00919423459120

                                                               

                                                             

OBJECTIVE

      To be enthusiastic and innovative as a part of initiative oriented and involving design/research team in VLSI, Nanotechnology, MEMS, Analog Mixed Signal design area.

 

EDUCATION

·       Jawaharlal Nehru Engineering College (JNEC), Aurangabad

         Dr BAM University, established in 1958, Maharashtra, India.        (Govt. of India Scholarship)

               Bachelor of Engineering in Electronics & Telecommunication (2001-2005)          A+                    67.2%(GPA 3.7/4)

·       Jawahar Navodaya Vidyalaya, Basamathnagar (Govt. of India HRD Scholarship)

          AISSCE, CBSE (10+2) (1999-2001)                                                                                  A+                                           76.4%

             AISSE, CBSE (10) (1999)                                                                                                     A                                              72.6%

 

 

AREAS OF INTEREST

       VLSI, Nanoelectronics, Analog Mixed Signal Design, Circuits, Devices, MEMS.

 

SKILLS

VLSI CAD Tools

 Agilent’s ADS Momentum ,  Tanner EDA tool

Software tools

MATLAB, Xilinx (VHDL), Active-HDL

Operating System

Unix, Linux, Windows NT/98/XP

Languages/HDL

C, C++, Assembly x86, VHDL, JAVA, J2EE, SQL

Other Skill areas

VLSI, Analog Mixed Signal Design, VCO, RF MEMS

PROJECTS

·       Collateral Allocation Management, JPMC*(Software Project)                                           Cognizant Technology Solutions

·       Profile Seeker, JPMC (Software Project)                                                                               Cognizant Technology Solutions

·       Low Phase Noise Wideband VCO using MEMS                                                                                

·       Wireless Point-to-Point Digital Audio-Video-Data Terminal         (Idea selected for Fabrication under India Chip Program, SCL*)

·       Bandgap bias network circuit                                           (Idea selected for Fabrication under India Chip Program, SCL*)

·       VCO for 3G/ 4G Wireless Communication, (BE Final year project )                                                                         Apr 2005

·       Wireless Stepper motor control-JNEC IEEE Student Project Contest.                                                                    Apr 2004

·       Cam less Valve Train -TECHFEST 2003, IIT Bombay.                                                                                                Jan 2003

·       DSP-FPGA Codesign for industrial Applications                                                                                                          Jan 2004

·       Oil Temperature Controller.-State level project contest.                                                                                              Nov 2003

* SCL-Semiconductor Complex Ltd., Govt. of India Enterprise

* JPMC- JPMorgan Chase & Co. (NYSE: JPM) is a leading global financial services firm with assets of $1.3 trillion and operations in more than 50 countries.

 

ACHIEVEMENTS/ AWARDS

·          Outstanding Engineering Student award, IEEE, 2004.

·          Outstanding engineering student, Dr B.A.M. University, 2003-04.

·          Nominated for Larry K. Wilson RAB IEEE R10 Award, 2004.

·          LONAR RATNA, Award for Scientific Contribution for development of Lonar Crater.

·          First Prize: IMS -2005 (Indian Microelectronics Society Conference).

·          First Prize: UG/PG Student Contest 2004, IEEE Communication Society.

·          First Prize: Hardware/software Project Contest, VIT IEEE SB, 2005.

·          Consolation prize, Open Hardware contest, IIT Bombay-TECHFEST 2003.

·          Finalist in Prof. K. Shankar Project Contest, IEEE Bombay Section 2004 & 2005.

·          Semifinalist - CSIDC-2004 (Computer Society International Design Contest).

                                & CSIDC 2005, Role-Team Leader.

·          Finalist at IIT Madras SHAASTRA 2003, Open Hardware, Project-X.

·          First Prize: State level Technical Quest, VIIT IEEE, 2002.

 

PUBLICATIONS

·     “Low Phase Noise Wideband VCO using MEMS”, presented in 48th IEEE Midwest International Symposium on Circuits and held at Cincinnati, Ohio, USA 7-10 Aug 2005 (MWSCAS 2005), MEMS I.

·        “Low Phase Noise Fully Integrated VCO”, presented in Research Scholars Forum, 18th IEEE International Conference on VLSI Design 2005, Kolkata, 3-5 Jan 2005.

·       “Supplier Evaluation for Part Procurement Using ISA”, presented in ICSCI-2005 (International Conference on Systematics, Cybernatics and Informatics Jan 2005), Pentagram research center, Hyderabad, Page 534-539 Vol.1

·    “ECVAS for Camless Engine”, presented in IMAE-2005 (IEEE International conference on Multidisciplinary of Engineering), Jan 2005, IEEE Bombay Section, Page 50.

·       “RF MEMS for Wireless Communication”, presented at K-SHANKAR Paper Competition, IEEE Bombay, 2 Apr 2005.

·    “VCO using MEMS Capacitor” presented in IMS (Indian Microelectronics Society Conference)-2005, 18-19 Feb 2005, Chandigarh.

·     “Stampede Warning and Protection System for Crowded and Congested places of Social Importance”, selected for CSIDC ’05 and K-Shankar Project Competition ’04, IEEE Bombay Section. 

·          “Programming FPGA’s using Handel- C”, presented at ‘SHAASTRA’, IIT Madras, 10 Oct 03.

·          "Sixth Sense Tutoring System- An ITS", selected for publication in ICSCI-2007 (International Conference on Systematics, Cybernatics and Informatics Jan 2007), Pentagram Research Centre, Hyderabad.

 

TRAINING/ WORK EXPERIENCE

·          Programmer Analyst , Cognizant Technology Solutions, Pune

·          Rexcorp Nanotech – Working as a “MEMS Technical Expert”. (Part time)

·          NASA: Worked with NASA team at Lonar  (Project Leader: Prof. Horton Newsom )

Role: Electronics and Communication related work like Mapping through GPS, Lonar Crater Study- relevance for finding out origin of universe

Participation in and contributed to “Deep Impact Mission-2004”, NASA.

Participation in and contributed to MARS Exploration Rover-2003 Mission”, NASA. 

·          Ambekar Associates- FPGA board development, Embedded application development.

·          Zoology Dept, Dr. B.A.M. University - Electro neurophysiology project.

 

MEMBERSHIPS 

·          Chairman of JNEC IEEE Student Branch 2003-05, Founder -JNEC IEEE Students Association.

·          Member of VSI (VLSI Society of India), IMS (Indian Microelectronics Society), IEEE Communication Society.

·          Chairman of JNEC ISTE Student Chapter 2003-04.

 

MISCELLANEOUS

·          Delivered talks on Analog Mixed signal design, IEEE Standards, Research trends in Electronics & Communication related topics in JNEC Auditorium.

·          Participated in large number of Conferences (IEEE, VLSI, and Embedded Systems) and presented many technical papers.