I am currently working as a Lead Design Engineer in Tensilica R&D division at Cadence Design Systems. My primary responsibilities at Cadence include leading the DSP engineering efforts (encompassing ISA extensions and micro-architecture optimization) on the Tensilica Fusion DSP processor targeted for the Internet-of-Things (IoT) and wearables applications. I have also worked on the design of high-performance DSP cores for baseband processing.

I received my Ph.D. degree in Electrical and Computer Engineering at Rice University in May 2014. My Ph.D. dissertation was in the emerging domain of inexact or approximate computing and my advisor was Prof. Krishna Palem. My research focused on developing and validating (through two ASIC chip fabrications) novel techniques to realize energy parsimonious "inexact" circuits, which could achieve upto an order of magnitude cost (energy, delay and/or area) savings by facilitating perceptually- and statistically-tolerable loss of output accuracy. As a part of my Ph.D, I spent a significant portion of my time working at the Swiss Center for Electronics and Microtechnology (CSEM SA), Switzerland collaborating with Prof.Christian Enz and Prof.Christian Piguet as well as at the Nanyang Technology University (NTU) , Singapore.

I have obtained my Master of Science (MS-Thesis) in Electrical and Computer Engineering from Rice University in May 2011. My thesis was titled Implementing Energy Parsimonious Circuits through Inexact Designs and was focussed on providing an initial foray into design techniques for realization of inexact circuits with zero (hardware) overhead. During this time, I have also worked on evaluating the sustainability of Information and Communication Technology (ICT) devices along with Prof. Christopher Bronk and Prof. Palem and also, was actively involved in the I-Slate project during its inception.

I obtained my Bachelor's degree (B.Tech) in Electronics and Communication Engineering (ECE) with honors in VLSI and Embedded Systems Design from International Institute of Information Technology, Hyderabad (IIIT-H) in May 2008. My undergraduate thesis was focussed on developing efficient arithmetic units to realize a high-speed and low-power Arithmetic and Logic Unit (ALU) with emphasis on using alternative number systems such as Residue number system and Redundant binary number system.