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Angada B. Sachid

Assistant Project Scientist, Electrical Engineering, University of California, Berkeley, CA, USA

Affiliate, Electronic Materials Program, Lawrence Berkeley National Laboratory, Berkeley, CA, USA

550 Sutardja Dai Hall, Desk 091, Berkeley, CA, USA 94720

Email: angada [AT] berkeley [DOT] edu


Research Areas
  • Group IV, III-V and 2D semiconductors
  • Nanoscale semiconductor devices
    • FinFET, Ultra-thin body FETs, Gate all around FETs
  • Steep subthreshold FETs
    • Negative capacitance FET
    • Tunnel FET
  • Nanoscale memory devices
    • Static Random-Access Memory (SRAM) 
    • Crosspoint memory 
    • Ferroelectric memory
  • Technology-circuit co-design
  • High-performance and low-energy circuits
  • Monolithic 3D Integration
    • Low thermal budget integration
    • Integration of Silicon CMOS and novel materials like Transition Metal Di-Chalcogenides
  • Semiconductor device reliability and noise
    • Negative bias temperature instability
    • Random telegraphic noise, 1/f noise
  • Device modeling and simulation
    • Technology Computer-Aided Design (TCAD)
    • Analytical and compact modeling



Ph.D. Indian Institute of Technology Bombay, India, 2010


Thesis: Technology-Circuit Co-design using FinFETs for Sub-22 nm Nodes


B. Tech. National Institute of Technology, Kurukshetra, India, 2003

Specialization: Electronics and Communication Engineering




Publications: >50; >800 citations; h-index: 14 (Google Scholar)


Selected Publications
  1. Angada B. Sachid, Min-Cheng Chen, Chenming Hu, "Bulk FinFET with Low-k Spacers for Continued Scaling," IEEE Transactions on Electron Devices, Vol. 64, No. 4, pp. 1861-1864, April 2017
  2. Angada B. Sachid, Yao-Min Huang, Yi-Ju Chen, Darsen D. Lu, Min-Cheng Chen, Chenming Hu, "FinFET with Encased Air-Gap Spacers for High-Performance and Low-Energy Circuits," IEEE Electron Device Letters, Vol. 38, No. 1, pp. 16-19, January 2017 (Highlighted on the cover)
  3. Sujay B Desai, Surabhi R Madhvapathy, Angada B Sachid, Juan Pablo Llinas, Qingxiao Wang, Geun Ho Ahn, Gregory Pitner, Moon J Kim, Jeffrey Bokor, Chenming Hu, H-S Philip Wong, Ali Javey, "MoS2 transistors with 1-nanometer gate lengths," Science, Vol. 354, Issue. 6308, pp. 99-102, 2016 [Highlighted in: MIT Technology ReviewScience Alertphys[dot]orgLawrence Berkeley Lab News Letter; EE TimesSemiconductor TodayElectronics Weekly; Compound SemiIndia Live TodayZMEScience; La Rampa di Napoli; Knowridge Science Report; BigFuture; NorCal News; EE News Europe; Engadget; Hardware Zone; Kurzweil AI; Hexus; HPC Wire; PC Games; Raw Story; Futurism; Electronics Lab
  4. Angada B. Sachid, Mahmut Tosun, Sujay B. Desai, Ching-yi Hsu, Der-Hsien Lien, Surabhi R. Madhvapathy, Yu-Ze Chen, Mark Hettick, Jeong Seuk Kang, Yuping Zeng, Jr-Hau He, Edward Yi Chang, Yu-Lun Chueh, Ali Javey, Chenming Hu, "Monolithic 3D CMOS using Layered Semiconductors," Advanced Materials, 2016
  5. Angada B. Sachid, Min-Cheng Chen, Chenming Hu, "FinFET with High-k Spacers for Improved Drive Current," IEEE Electron Device Letters, Vol. 37, No. 7, pp. 835-838, July 2016 
  6. Angada B. Sachid, Chenming Hu, "Denser and More Stable SRAM using FinFETs with Multiple Fin Heights," Vol. 59, Issue 8, IEEE Transactions on Electron Devices, August 2012 [Highlighted in: IEEE Spectrum]
  7. Angada B. Sachid, Manoj C. R., Dinesh K. Sharma, V. Ramgopal Rao, "Gate-fringe induced barrier lowering in underlap FinFET structures and its optimization," IEEE Electron Device Letters, Vol. 29, Issue 1, pp.128-130, January 2008
  8. Angada B. Sachid, Roswald Francis, Maryam Shojaei Baghini, Dinesh K. Sharma, Karl-Heinz Bach, Reinhard Mahnkopf, V. Ramgopal Rao, "Sub-20 nm gate length FinFET design: Can high-κ spacers make a difference?," International Electron Devices Meeting (IEDM), San Fransisco, California, USA, December 15-17, 2008, pp. 697-700
  9. Angada B. Sachid, Chenming Hu, "Impact of Channel Doping on the Device and NBTI Performance in FinFETs for Low Power Applications," IEEE VLSI-Technology, Systems and Applications (VLSI-TSA), Hsinchu, Taiwan, April 28-30 2014, pp. 1-2 
  10. Angada B. Sachid, Sourabh Khandelwal, Chenming Hu,"Body-Bias Effect in SOI FinFET for Low-Power Applications: Gate Length Dependence," IEEE VLSI-Technology, Systems and Applications (VLSI-TSA), Hsinchu, Taiwan, April 28-30 2014, pp. 1-2 
  11. Angada B. Sachid, Hui Fang, Ali Javey, Chenming Hu, "Series Resistance and Mobility in Mechanically-Exfoliated Layered Transition Metal Dichalcogenide MOSFETs," IEEE VLSI-Technology, Systems and Applications (VLSI-TSA), Hsinchu, Taiwan, April 28-30 2014, pp. 1-2 
  12. Angada B. Sachid, Navid Paydovosi, Sourabh Khandelwal, Chenming Hu, "Multi-Gate MOSFET with Electrically Tunable VT for Power Management," International Semiconductor Device Research Symposium, Dec 11-13 2013, Maryland, USA 
  13. Angada B. Sachid, Chenming Hu, "A Little Known Benefit of FinFET over Planar MOSFET in High-Performance Circuits at Advanced Technology Nodes", IEEE International SOI Conference, Napa, CA, USA, October 2012 
  14. Angada B. Sachid, Chenming Hu, "Denser and More Stable FinFET SRAM using Multiple Fin Heights," International Semiconductor Device Research Symposium, Maryland, USA, December 2011 [Highlighted in: IEEE Spectrum]
  15. Angada B. Sachid, Pallavi Paliwal, Sanjay Joshi, Maryam Shojaei, Dinesh Sharma and V. Ramgopal Rao, "Circuit Optimization at 22nm Technology Node", Proceedings of the 25th International Conference on VLSI Design, January 7-11, 2012, Hyderabad, India
  16. Angada B. Sachid, Maryam Shojaei Baghini, Dinesh K. Sharma, V. Ramgopal Rao, "Alternate scaling strategies for multi-gate FETs for high-performance and low-power applications," IEEE International SoC Design Conference (ISOCC), 2010, pp. 256-259
  17. Angada B. Sachid, Maryam Shojaei Baghini, Dinesh K. Sharma, V. Ramgopal Rao, "Technology-aware design using FinFETs for sub-22 nm technology nodes," Invited Paper, International Workshop on Physics of Semiconductor Devices (IWPSD), December 2009
  18. Angada B. Sachid, Rajesh A. Thakker, Chaitanya Sathe, Maryam Shojaei Baghini, Dinesh K. Sharma, V. Ramgopal Rao, Mahesh B. Patil, "Auto-BET-AMS: An Automated Device and Circuit Optimization Platform to Benchmark Emerging Technologies for Performance and Variability using an Analog and Mixed-Signal Design Framework," accepted at International Symposium on Quality Electronic Design (ISQED), 22-24 March 2010, San Jose, CA, USA
  19. Angada B. Sachid, Giri S. Kulkarni, Maryam Shojaei Baghini, Dinesh K. Sharma, V. Ramgopal Rao, "Highly robust planar double-gate MOSFET device and SRAM cell immune to gate misalignment and process variations," International Workshop on Electron Devices and Semiconductor Technology (IEDST), June 1-2, 2009, Mumbai, India
  20. Angada B. Sachid, Mayank Srivastava, Rajesh A. Thakker, Maryam Shojaei Baghini, Dinesh K. Sharma, V. Ramgopal Rao, Mahesh B. Patil, "Technology-aware design (TAD) for sub-45 nm CMOS technologies," Intel Asia Academic Forum, Taipei, Taiwan, 20-23 October 2008. (Won the Best Research Paper award in Circuit Design category)