Rethinking Digital Design
As discussed in the CPU DB, the energy per switch of a transistor in post 45nm processes is scaling at a slower rate. This means that the only way to increase hardware performance while remaining energy efficient is to decrease the energy required for operations. The best way to do this is by adding custom hardware, which can complete an algorithm or a class of algorithms hundreds-thousands of times more efficiently than a general purpose processor . The cost of even just developing a custom system, however, is skyrocketing, reaching $60-$80 million for a new 32nm chip . The Rethinking Digital Design project is about developing ways to raise the level of abstraction for designing an chip . My research in particular looks at ways to make SoC integration more efficient, and at ways to automatically generate the C drivers and APIs needed to drive the custom hardware in an SoC design.
Today an SoC designer inevitably runs into an interface mismatch between the various IP blocks in their system. While many bus standards have been developed to standardize IP interfaces, it is unlikely that all blocks in a system will use the same standard. This bus diversity is often caused by evolution of these standards. While using a newer standard my give benefits in performance and energy, designers often need to use an older IP block with the previous generation bus interface. This problem is fundamental to SoC design: the designer of the block cannot know about the environment where that block will be used because that environment does not exist when the block is created.
As a solution to this problem, I proposed and built a parameterized bus interface generator which can connect the interface signals in each IP block to the current bus abstraction. Since the mapping between the IP block and the system bus is done algorithmically, it will be maintained as both the system bus and the parameterized interface evolve to support more complex operations. In other words, this parameterized IP interface allows an IP block to connect to the system interconnect's interface in existing systems while offering the flexibility to adapt as bus standards evolve over time.
1. Rehan Hameed, Wajahat Qadeer, Megan Wachs, Omid Azizi, Alex Solomatnikov, Benjamin C. Lee, Stephen Richardson, Christos Kozyrakis, and Mark Horowitz. 2010. "Understanding sources of inefficiency in general-purpose chips." in Proceedings of the 37th annual international symposium on Computer architecture (ISCA '10). ACM, New York, NY, USA, 37-47. http://doi.acm.org/10.1145/1815961.1815968
2. R. E. Collett, "Executive Session: How to address today's growing system complexity," in DATE ’10: Conference on Design, Automation and Test in Europe, March 2010.
3. M. Keating, Third revolution: The search for scalable code-based design.
4. Ofer Shacham, Megan Wachs, Andrew Danowitz, Sameh Galal, John Brunhaver, Wajahat Qadeer, Sabarish Sankaranarayanan, Artem Vassiliev, Stephen Richardson, and Mark Horowitz. 2012. Avoiding game over: bringing design to the next level. In Proceedings of the 49th Annual Design Automation Conference (DAC '12). ACM, New York, NY, USA, 623-629. http://doi.acm.org/10.1145/2228360.2228472