Amitabha Roy

I am a post-doctoral researcher at LABOS in EPFL, where I am primarily responsible for the X-Stream graph processing systemMy interests span systems, computer architecture and algorithms. I enjoy studying, building and tuning systems to solve challenging niche problems. Some of the interesting things I've done are building a graph processing system that tackles tens of billions of edges on a single machine, developed a completely transparent software transactional memory implementation for x86 machine code and developed a parallel algorithm for verifying the x86 memory consistency model that is used by Intel to verify their multicore products before they are shipped to customers.   

Contact: amitabha dot roy at epfl dot ch                                  amitabha dot roy at gmail dot com 


Publications [Google Scholar  DBLP]


Amitabha Roy, Ivo Mihailovic, Willy Zwaenepoel. 

Jiaqing Du, Sameh Elnikety, Amitabha Roy, Willy Zwaenepoel. 

Amitabha Roy, Steven Hand, Tim Harris. 
Weak Atomicity for the x86 Memory Consistency Model, Journal of Parallel and Distributed Computing, 72(2012) [preprint]

Amitabha Roy, Steven Hand, Tim Harris. 

Amitabha Roy, Steven Hand, Tim Harris. 

Amitabha Roy, Stephan Zeisset, Charles J. Fleckenstein,John C. Huang. 

Amitabha Roy, K. Gopinath. 

Short Papers/Early Ideas


Jasmina Malicevic, Amitabha Roy, Willy Zwaenepoel. Scale-up Graph Processing in the Cloud: Challenges and Solutions, CloudDP 2014

Amitabha Roy, Timothy Jones. ALLARM: Optimizing Sparse Directories for Thread-Local Data, DATE 2014

Eiko Yoneki, Amitabha Roy. Scale-up Graph Processing: A Storage-centric View, GRADES 2013

Amitabha Roy, Steven Hand, Tim Harris. Exploring the Limits of Disjoint Access Parallelism, HotPar 2009

Technical Reports

Amitabha Roy, Karthik Nilakant, Valentin Dalibard, Eiko Yoneki. Mitigating I/O latency in SSD-based graph traversal, UCAM-CL-TR-843

Eiko Yoneki, Amitabha Roy. A Unified Graph Query Layer for Multiple Databases, UCAM-CL-TR 2012

Amitabha Roy. Memory Hierarchy Sensitive Graph Layout, Arxiv 2012

Grants/Scholarships/Awards

I held a grant from the Hasler foundation for "Cache conscious graph processing", which funded some of the work on X-Stream.
I held a Nehru-Cambridge scholarship while a PhD student at Cambridge.
I held a BoGS Lundgren award while a PhD student at Cambridge.
I was awarded support from the Freshwater fund at Emmanuel College, while a PhD student at Cambridge.
I won a divisional award at Intel for designing an algorithm to verify that processors conform to the x86 memory consistency model. 

Teaching/Community Service 

I have supervised summer interns and assist in the supervision of PhD students in LABOS.

I've acted as a TA for a graduate level operating systems course, supervised undergraduate students at Cambridge for the Part II Comparative Architectures course and delivered part of a mini-course on lock-free programming and transactional memory. I have also supervised an MPhil thesis at the Computer Laboratory.
 
I am an occasional reviewer for Computing Reviews.

Background

I spent a little less than a year as a post-doc in the Computer Architecture Group at the University of Cambridge Computer Laboratory, where I worked on a technique to adapt directory controllers for thread-private data with Timothy Jones. Simultaneously I also worked with Eiko Yoneki in the Systems Research Group on ways to mitigate IO stalls when processing large graphs. I continue to collaborate with Eiko on the Graphcam project.

I spent a short while at Acunu where I worked on analysing the performance of their filesystem.
 
I finished my PhD in June 2011 from the Networks and Operating Systems (NetOS) research group at the Computer Laboratory in the University of Cambridge. I was supervised by Steven Hand and Tim Harris. My PhD thesis, titled "Software lock elision for x86 machine code", argues for separation of mechanism and policy in the context of software transactional memory. It presents the design and implementation of a system that can be used to automatically elide legacy locks in x86 machine code. Transactional memory therefore becomes an optional mechanism for synchronization, with legacy locks or atomic blocks implemented using legacy locks being used to specify synchronization policy. A talk I've given describes many of the basic ideas.

I used to work at Intel till August 2007 where I worked for some time on memory consistency verification and later did performance modeling and analysis of CPUs. Among other things, I designed a parallel algorithm to verify memory consistency test results using graphs, which is widely used in post-silicon validation at Intel. More work related things can be found in my linkedin profile.

I got my Master's degree in computer science from the Computer Science department at IISc Bangalore. While there, I worked in the Computer Architecture and Systems Laboratory under Prof. K. Gopinath on probabilistic timed automata for 802.11 networks.
 
I got my undergraduate engineering degree at Jadavpur University in the Department of Computer Science and Engineering.