Ph.D. Dissertation
  • Proactive Energy Management Techniques for Smart Building and Compute Server Architectures, Cornell University, December 2017.

  • “Dynamic GPGPU Power Management using Adaptive Model Predictive Control,” Abhinandan Majumdar, Leonardo Piga, Indrani Paul, Joseph L. Greathouse, Wei Huang and David H. Albonesi, 23rd IEEE Symposium on High Performance Computer Architecture (HPCA 2017), Austin, February 2017 (acceptance rate: 22%). [URL][paper][presentation]
  • "Characterizing the Benefits and Limitations of Smart Building Meeting Room Scheduling", A. Majumdar, Z. Zhang, D. H. Albonesi, The 7th ACM/IEEE International Conference on Cyber-Physical Systems, Vienna, Austria, April 2016 (acceptance rate: 28%). [URL][paper][presentation]
  • "A Taxonomy of GPGPU Performance Scaling", A. Majumdar, G. Wu, K. Dev, J. L. Greathouse, I. Paul, W. Huang, A. Venugopal, L. Piga, C. Freitag, and S. Puthoor, IEEE International Symposium on Workload Characterization (IISWC 2015), Atlanta, GA, October 2015 (acceptance rate: 48%). [URL][paper][poster]
  • "Energy-Comfort Optimization using Discomfort History and Probabilistic Occupancy Prediction", A. Majumdar, J. L. Setter, J. R. Dobbs, B. M. Hencey, and D. H. Albonesi, International Green Computing Conference, Dallas, November 2014 (acceptance 36%). [URL] [paper][presentation]
  • "Energy-Aware Meeting Scheduling Algorithms for Smart Buildings", A. Majumdar, D. H. Albonesi and P. Bose, 4th ACM Workshop On Embedded Sensing Systems For Energy-Efficiency In Buildings (BuildSys 2012), Toronto, November 2012, co-located with Sensys 2012 (acceptance rate: 32%). [URL] [paper] [presentation]
  • "An FPGA-based Parallel Accelerator for Semantic Search", A. MajumdarS. Cadambi, S. T. Chakradhar and H. P. Graf, 9th IEEE Symposium on Application Specific Processors (SASP 2011), San Diego, June 2011 ), co-located with Design Automation Conference (DAC) 2011 (acceptance rate: 29%). [URL] [paper] [presentation]
  • "A Programmable Parallel Accelerator for Learning and Classification", S. Cadambi, A. Majumdar, M. Becchi, S. T. Chakradhar and H. P. Graf, The Nineteenth International Conference on Parallel Architectures and Compilation Techniques (PACT 2010), Vienna, Austria, September 2010 (acceptance rate: 17%). [URL] [paper] [presentation]

  • "A Massively Parallel, Energy Efficient Programmable Accelerator for Learning and Classification", A. Majumdar, S. Cadambi, M. Becchi, S. T. Chakradhar and H. P. Graf, ACM Transactions of Architecture and Code OptimizationVol. 9 Issue 1, March 2012. [URL]
  • "An Energy-Efficient Heterogeneous System for Embedded Learning and Classification"A. MajumdarS. Cadambi, and S. T. Chakradhar, IEEE Embedded Systems Letter, Vol. 3, Issue 1, March 2011. [URL][paper]

Book Chapters
  • "Massive SVM Parallelization using Hardware Accelerators", I. Durdanovic, E. Cosatto, H. P. Graf, S. Cadambi, V. Jakkula, S. T. Chakradhar and A. Majumdar, Scaling Up Machine Learning, Cambridge University Press book, 2010, edited by Ron Bekkerman, Misha Bilenko, and John Langford. [URL]

  • "Massively Parallel Low-Power Processor for Learning and Classification", S. Cadambi, B. Bai, I. Melvin, A. Majumdar, I. Durdanovic, H. P. Graf, and S. T. Chakradhar, Neural Information Processing Systems (NIPS 2009), Vancover, B.C., December 2009. [poster]