Yong Li's Homepage

About Me

Yong Li obtained his PhD degree in Computer Engineering from University of Pittsburgh. He has more than 20 research and academic publications in prestigious conferences and journals in the field of high performance and scalable computer architecture, distributed systems, Kubernetes, etc. He has been a founding member of a Silicon Valley based startup, initiated an open source project, and hold a US patent related to Kubernetes. He has intensive R&D and product development experience in leading companies in the industry such as Intel, VMware, and Huawei.

中文介绍：

李勇拥有匹兹堡大学计算机工程博士学位, 并在包括高性能计算机体系结构，并行分布式计算，Kubernetes 等多个相关领域发表过超过20篇研究及学术论文。他曾参与一家硅谷公司的早期创业，发起过开源项目，拥有一项与Kubernetes相关的原创性专利。 他有着丰富的研究和产品开发经验，曾就职于业界领先的公司比如英特尔，微睿，华为等。

Interests

Building highly scalable and performing systems that have a practical impact. Working or seeking opportunities to work with great people on addressing challenge problems.

Education

    • Dec 2010 ~ Dec 2013: PhD in Computer Engineering under the supervision of Prof. Alex K. Jones and Rami Melhem

    • Jan 2009 ~ Dec 2010: Awarded the degree of Master of Science in Computer Engineering, University of Pittsburgh, Dec. 12, 2010.

    • Sep 2001 ~ Jul 2005: Telecommunication Engineering, Chongqing University. Awarded merit-based scholarships for 7 out of the 8 semesters and graduated with first honor.

Entrepreneurship

  • Founder of Y&R Computing, an organization I found where I use my spare time to provide solutions and designs for distributed systems, software consulting services, early support (e.g., making coding standard, talent acquisition, frameworking/prototyping initial software system) for startup companies.

    • Employee #1, architect (part time), and angel investor for NewsOnChat Inc., a social media startup company based in silicon valley.

Industrial Experience

    • Dec 2013 ~ Present: Work at VMware as a Staff Engineer on optimizing data center management software (vSphere) and tools. My duty was to identify the bottleneck of the full stack system and improve performance and scalability of our products. My optimizations and work have improved performance of certain components by 2- to 100X. Recognized as outstanding engineer and achieved "always exceed the expectation" recognition.

    • Jun 2005 ~ Jul 2007: Worked at Huawei Technologies as a system engineer responsible for designing, optimizing, debugging and testing network topology and infrastructure systems. Achieved A evaluation (top 5%) for 4 out of 8 quarters, and was recognized as an excellent employee and an outstanding engineer.

Internship and Summer Employments

    • Jun 2011 ~ Jul 2011: Worked as a research intern in the Embedded Architecture Research Lab, Intel, where I designed, modeled and built parallel data center based on Hadoop, HBase, etc.

    • Apr 2010 ~ Jun 2010: Selected by the School of Law, University of Pittsburgh, to work on a database system that is capable of handing terabytes images and case documents. A web-interface was also implemented to facilitate the access to the database.

    • Jun 2010 ~ Sep 2010: Funded by the National Centers for Disease Control and Prevention (CDC) for software development for a TI MSP430 based vibration dosimeter that connects to a digital sensor and collects the sensed data to a MicroSD card.

Research Publications

  • Lei Liu, Hao Yang, Yong Li, Mengyao Xie, Lian Li, Chenggang Wu. "Memos: A Full Stack Framework for Hybrid Memory Management in Modern Operating System" The 34th IEEE International Conference on Computer Design (ICCD), 2016. iccd-16

  • Lei Liu, Yong Li, Chen Ding, Hao Yang, Chengyong Wu "Rethinking Memory Management in Modern Operating System: Horizontal, Vertical or Random?" The IEEE Transactions on Computers (TC), 2016. tc-16

  • Yaojun Zhang, Yong Li, Zhenyu Sun, Hai Li, Yiran Chen, Alex K. Jones "Read Performance: The Newest Barrier in Scaled STT-RAM" IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2015. tvlsi-15

    • Yong Li, Haifeng Xu, Rami Melhem, Alex K. Jones "Space Oblivious Compression: Power Reduction for Non-Volatile Main Memories" GLSVLSI '15 Proceedings of the 25th edition on Great Lakes Symposium on VLSI, 2015. glsvlsi-15

  • Haifeng Xu, Yong Li, Rami Melhem, Alex K. Jones "Multilane Racetrack Caches: Improving Efficiency through Compression and Independent Shifting" Design Automation Conference (ASP-DAC), 20th Asia and South Pacific, 2015. aspdac-15

  • Haifeng Xu, Yong Li, William O. Collinge, Laura A. Schaefer, Melissa M. Bilec, Alex K. Jones, Amy E. Landis "Improving Efficiency of Wireless Sensor Networks through Lightweight In-memory Compression" Green Computing Conference and Sustainable Computing Conference (IGSC), 2015. igsc-15

    • Lei Liu, Yong Li, Zehan Cui, et. al. "Going Vertical in Memory Management: Handling Multiplicity by Multi-policy" The 41st International Symposium on Computer Architecture (ISCA), 2014. isca-14-liu

    • Lei Liu, Zehan Cui, Yong Li, et. al. "BPM/BPM+: Software-based Dynamic Memory Partitioning Mechanisms for Mitigating DRAM Bank-/Channel-level Interferences in Multicore Systems" The ACM Transactions on Architecture and Code Optimization (TACO), 2014. taco-14-liu

    • Xiaoxiao Liu, Yong Li, Yaojun Zhang, Alex K. Jones, and Yiran Chen "STD-TLB: A STT-RAM-based Dynamically-configurable Translation Lookaside Buffer for GPU Architectures" The 19th Asia and South Pacic Design Automation Conference (ASP-DAC), Jan, 2014. aspdac-14-liu

    • Mengjie Mao, Guangyu Sun, Yong Li, Alex K. Jones and Yiran Chen "Prefetching Techniques for STT-RAM based Last-level Cache in CMP Systems" The 19th Asia and South Pacic Design Automation Conference (ASP-DAC), Jan, 2014.aspdac-14-mao

    • Yong Li, Yaojun Zhang, Hai Li, Yiran Chen, and Alex K. Jones "C1C: A Configurable, Compiler-Guided STT-RAM L1 Cache" The ACM Transactions on Architecture and Code Optimization (TACO), 2013. taco-13

    • Yong Li, Rami Melhem, and Alex K. Jones "A Practical Data Classication Framework for Scalable and High Performance Chip-Multiprocessors" The IEEE Transactions on Computers (TC), 2013. tc-13

    • Yong Li, Rami Melhem, and Alex K. Jones "PS-TLB: Leveraging Page Classification Information for Fast, Scalable and Efficient Translation" The ACM Transactions on Architecture and Code Optimization (TACO), 2012. taco-12

    • Yong Li, and Alex K. Jones "Cross-layer Techniques for Optimizing Systems Utilizing Memories with Asymmetric Access Characteristics" IEEE Annual Symposium on VLSI (ISVLSI), Aug. 2012, Amherst, USA. isvlsi-12

    • Yong Li, Rami Melhem, and Alex K. Jones "Practically Private: Enabling High Performance CMPs Through Compiler-assisted Data Classification" Proceedings of the 21st International Conference on Parallel Architectures and Compilation Techniques (PACT), Sep. 2012, Minneapolis, MN, USA. pact-12

    • Yong Li, Yiran Chen, and Alex K. Jones "A Software Approach for Combating Asymmetries of Non-Volatile Memories" International Symposium on Low Power Electronics and Design (ISLPED) , July, 2012, Redondo Beach, CA, USA. islped-12

    • Yong Li, Yaojun Zhang, Yiran Chen, and Alex K. Jones "Combating Write Penalties Using Software Dispatch for On-chip MRAM Integration" IEEE Embedded System Letters (ESL), Special Issue on Novel Memory Architecture and Organization, Apr. 2012. esl-12

    • Yaojun Zhang, Yong Li, Yiran Chen, and Alex K. Jones "Asymmetry of MTJ Switching and Its Implication to the STT-RAM Designs" Design, Automation & Test in Europe (DATE), Mar. 2012, Dresden, Germany. date-12

    • Yong Li, Ahmed Abousamra, Rami Melhem, and Alex K. Jones "Compiler-Assisted Data Distribution and Network Configuration for Chip Multiprocessors" IEEE Transactions on Parallel and Distributed Systems (TPDS), Dec. 2011. tpds-11

    • Yong Li, Rami Melhem, and Alex K. Jones "Leveraging Sharing in Second Level Translation-Lookaside Buffers for Chip Multiprocessors" IEEE Computer Architecture Letters (CAL), Dec. 2011. cal-11

    • Yong Li, Yiran Chen, and Alex K. Jones "Magnetic RAM Integration for CMPs using Hardware-Based Software-Optimized Dispatching" ICS Workshop on Emerging Supercomputing Technologies (WEST), May. 2011, Loews Ventana Canyon Resort, Tucson, Arizona, USA. west-11

    • Yong Li, Ahmed Abousamra, Rami Melhem, and Alex K. Jones "Compiler-assisted Data Distribution for Chip Multiprocessors" Proceedings of the 19th International Conference on Parallel Architectures and Compilation Techniques (PACT), Sep. 2010, Vienna, Austria. pact-10

    • Yong Li, Rami Melhem, and Alex K. Jones "Compiler-based data classification for hybrid caching" Proceedings of the 2010 Workshop on Interaction between Compilers and Computer Architecture (INTERACT), Mar. 2010, Pittsburgh, PA, USA.interact-10

Talks and Presentations

    • PS-TLB: Leveraging Page Classification Information for Fast, Scalable and Efficient Translation, International Conference on High-Performance and Embedded Architectures and Compilers (HiPEAC), Jan. 2013, Berlin, Germany.

    • Practically Private: Enabling High Performance CMPs Through Compiler-assisted Data Classification, International Conference on Parallel Architectures and Compilation Techniques (PACT), Sep. 2012, Minneapolis, MN, USA.

    • Compiler-assisted Data Distribution for Chip Multiprocessors, International Conference on Parallel Architectures and Compilation Techniques (PACT), Sep. 2010, Vienna, Austria.

    • Magnetic RAM Integration for CMPs using Hardware-Based Software-Optimized Dispatching, ICS Workshop on Emerging Supercomputing Technologies (WEST), May. 2011, Loews Ventana Canyon Resort, Tucson, Arizona, USA.

    • Compiler-based Data Classification for Hybrid Caching, ASPLOS Workshop on Interaction between Compilers and Computer Architectures, Mar. 2010, Pittsburgh, PA, USA.

Academic Services

    • HPCC Program Committee, 2015.

    • Technique Reviewer - ACM/EDAC/IEEE Design Automation Conference (DAC), 2013.

    • Technique Reviewer - IEEE International Parallel & Distributed Processing Symposium (IPDPS), 2013.

    • External Reviewer - IEEE/ACM International Symposium on Microarchitecture (MICRO), 2012.

    • Technique Reviewer - IEEE International Conference on Parallel Architectures and Compilation Techniques (PACT), 2012.

    • Technique Reviewer - ACM/EDAC/IEEE Design Automation Conference (DAC), 2012.

    • Technique Reviewer - IEEE International Conference on Parallel Processing (ICPP), 2012, 2011.

    • Journal Reviewer - IEEE Transactions on Computers (TC), 2011.

    • Journal Reviewer - ACM Transactions on Design Automation of Electronic Systems (TODAES), 2011.