The Home page of this website states that the goal is to show what goes on inside of Integrated Circuits... Here's the Page where that happens on a very simple scale...
The middle chip is a 7402, Quad 2-Input NOR Gate
The Middle Chip is a 7402: Quad 2 Input NOR Gate... It has 4 individual 2 input NOR gates
The Data Sheet information for the pinout of this chip is: 
Standard Quad, 2 Input NOR Gate
This is the sybolic representation of the inner workings of this chip. It does not show the circuit details ,just the logic cells available. Given that you are considering custom logic without going through the expense and effort of creating a custom ASIC, Now, you would most likely use a microcontroller for simple logic since they cost the same. Or if you need performance and a lot of logic then you would probably use an FPGA

The logic table and the sybol are covered...The Transistor details are covered pretty well on The NOR section and various other places all over the web...

For our example we will be creating an "Unbuffered" Individual NOR gate without ESD protection... NOR with input ESD protection
We are going to create a traditional 1x CMOS nor gate. 1x unit drive strength implies that the Gate will be built out of the smallest standard logic unit size transistors. A 2x unit drive strength would have twice the width on all transistors and a 4x would be 4 times the width of all transistors. See Unit_Sizes_and_On_Resistance and also Fanout

The mobility of the PMOS in most standard CMOS process until the past few years has been less than that of the NMOS devices, PMOS gate widths are scaled to have the same "On Resistance" 

For rise/fall time symmetry the total "pull up" path of the output is designed to be equal to the total "pull down" path. the NOR gate can be switched on with either NMOS device being activated (input high) but when both inputs are low the PMOS path must provide the same total resistance as a single NMOS. To create the same series resistance as a single NMOS unit the two PMOS devices must be 2 units wide so that each has 1/2 of a resistance unit. 

The Unit Sizing of a symmetric NOR gate
NOR Transistors on Schematic and Layout

The actual layout implementation will vary by purpose and designer.

This layout is good for this purpose of putting 4 identical logic gates in the same package.

This layout is not very good for standard cell designs because it is taller than other cells, like an inverter, would be. Stripes are used on both the NMOS and PMOS devices for standard cells designed to be used with automated place and route. 

Making the Connections for 1 of the 4, 2 input NOR gates
The this individual 2 Input NOR Gate is duplicated 4 times to make the Quad pack

Quad, 2 input NOR gate schematic implementation of simplified 7402
Adding a second metal layer to make the output routing connections the layout takes final shape and is ready to be wire bonded into the package
Simplified 7402 Quad, 2 Input NOR Gate
And then Comparing to the Datasheet pinout:
Datasheet Pinout overlaid on Layout
It's mentioned that this is a simplified version and as a student that always frustrated me because I felt the details being left out were what made the difference between the information being useful or just text book stuff. Mentioned above that this does not include ESD protection or additional buffering. The chip would actually work as-is, the output would self protect and with a few extra diodes on the input as pictured in the wikipedia entry you have a complete product, 40 years too late... 

Nobody would likely use to220 packaged individual PMOS(IRF9510) and NMOS(IRF510) to create a real quad, two input NOR circuit like the 7402... But here's what it would look like for just the sheer number of required devices vs a pre-packaged DIP
A (poor) comparison of the 16 FETs to make the same logic