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Hierarchy of an Integrated Circuit Schematic

Layers of Abstraction can get confusing.


In descending order.


Block Diagram level: Made up of Gates

Gate level: Each Gate is made from Transistors

Transistor level: Each transistor symbol corresponds to a physical transistor to be laid out

Physical layout level: The actual real world implementation.

Here is one option for a NAND Logic Gate Implementation. On the Left is the Schematic view that contains the abstracted transistors. In the middle is on potential layout option (Not very good for automated place and route). On the right is the symbol view that would be instantiated(placed) in another schematic to represent the transistor and layout view. 

One option for a NAND gate implementation
All represent the same logical operation of Not( A and B )... Well the layout isn't actually wired up, just the active devices placed...