Join our continuous, virtual community gathering on Zoom for insightful discussions on the progress made within Committees, SIGs, Task Groups, HCs and RISC-V Technical Community.

Recordings of the sessions will be accessible within 24 hours following the event.

Technical Sessions 2024 Schedule

RISC-V Community Sessions

Past Technical Sessions

José Moreira

Dr. José E. Moreira is a distinguished researcher at IBM, known for his significant contributions to high-performance systems and innovations in POWER processors. He is the chair of the RISC-V Vector SIG.

LinkedIn

Scalar, vector, matrix – the next stage in SIMD processing

For the last 50 years, vector processing has established itself as the technique of choice for improving performance of important computations. Once a unique feature of the world's top supercomputers, vector processing is now ubiquitous throughout the spectrum of computing systems. Yet, vector processing does not inherently offer any advantage in computational intensity over scalar processing. Multiplying two n-element vectors produces one operation per pair of input elements, just like multiplying two scalars. During the past few years we have seen the rise of a truly different form of computation, matrix processing. Consider the outer-product of two n-element vectors, which produces n^2 operations. This example of matrix processing has a fundamentally different computational intensity, that scales with the size of the vectors. Recent GPUs and now some CPUs are being augmented with dedicated matrix units that can perform some of these matrix computations directly. Matrix processing will not replace vector processing any more than vector processing has replaced scalar processing. Instead, it will open new ways on how computations are performed and create new opportunities for high-performance computers to make even deeper impacts on human activities. In this talk, we will revisit some of the fundamentals of matrix processing, and describe existing systems with matrix units, such as the IBM POWER10 processor. We will also discuss matrix processing in GPUs, which has become very popular, and explore what the near future holds for this powerful new computing model.

Thursday, November 2nd 2023 |  (Recording | Presentation)

Ravi Sahita

Principal Systems Security Architect at Rivos Inc. He is an expert in CPU/platform virtualization, trusted execution environments, and exploit prevention.

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Atish Kumar Patra

Atish is a Linux kernel engineer working at Rivos. He has worked on various features for RISC-V Linux kernel i.e. UEFI, early boot, virtualization and device drivers, confidential computing. He is also co-maintainer of SBI specification and OpenSBI project.

LinkedIn

Enabling Confidential Computing on RISC-V Platforms 

This session will describe the ongoing work the Security HC is doing through various task groups to enable confidential computing models on RISC-V platforms. We will describe where we are at with the Priv ISA, and non-ISA (HW and SW), and what we are working on. We will also explain how this work fits other industry standards to enable this new secure computing model.

Thursday, Sep 14th 2023 |  (Recording | Presentation)

Beeman Strong

Beeman works on RISC-V ISA and microarchitecture at Rivos, with a focus on performance monitoring, debug, and trace.  His RISC-V responsibilities include chairing the Performance Analysis SIG and the Control Transfer Records TG.  Beeman previously spent 25 years at Intel, including serving as Atom architect for trace and performance monitoring.

LinkedIn

Atish Kumar Patra

Atish is a Linux kernel engineer working at Rivos. He has worked on various features for RISC-V Linux kernel i.e. UEFI, early boot, virtualization and device drivers, confidential computing. He is also co-maintainer of SBI specification and OpenSBI project.

LinkedIn

RISC-V Performance Monitoring: Where we are and where we're going

In this session, we'll provide an overview of ISA extensions in flight that address competitive gaps in performance analysis capabilities, and the software enabling to support them. Further, we'll cover additional software enhancements that reduce profiling overhead and enable monitoring in critical sections.

Thursday, Aug 3rd 2023 | (Recording | Presentation)

Marc Karasek

Innovative Engineering Leader: Analytical, Adaptable, Skilled Mentor, with a Proven Track Record in Software Development, Open Source Contributions, Patents, and Industry Recognition.

LinkedIn

uMON Ramless Monitor for use in Chip Bring-up and Debug 

In bringing up a new SOC there are many challenges. You need a good part of the system up and running prior to having any kind of console/debug monitor. This is normally because you need a good part of the SOC functional before you can run code. uMON helps you to debug your SOC earlier in the process. uMON just requires a boot device, working uart and the SOC. It uses the registers in the SOC as a stack for input from the console(UART). It can then execute a number of commands (fill, dump, compare, etc..) that will allow you to debug the rest of the SOC.

Thursday, July 20th 2023 |  (Recording | Presentation)

Dr. Markku-Juhani O. Saarinen

Dr. Saarinen is a Staff Security Architect with PQShield (Oxford, UK) and a Professor of Practice (työelämäprofessori) at Tampere University (Finland). He holds a Ph.D. in Information Security (Cryptanalysis) from Royal Holloway, University of London (2009).

LinkedIn

RISC-V Cryptography and Hardware Security

In this session, Dr. Saarinen will explore the RISC-V ISA cryptography architecture, including its scalar and vector cryptography extensions, features, and entropy source. He'll also discuss future ISA extension plans such as Post-Quantum Cryptography, Full-Rounds AES, and Key Management. The primary focus is on how these cryptographic ISA extensions are designed to reduce latency and energy usage in networking and storage encryption operations, and eliminate side-channel vulnerabilities. Furthermore, he will address the security needs of mobile, IoT, and data center systems, focusing on platform security requirements, countermeasures, and testing methods. Finally, he will point to significant open-source projects like Caliptra and OpenTitan that are contributing to this field.

Thursday, June 29th 2023 |  (Presentation | Recording)

Daniel Maslowski

Daniel likes giving talks and workshops.

In his free time, he works on various software projects, especially operating systems and distributions, bringup and application firmware, with a focus on tooling, integration, and documentation.

He created Fiedka, the firmware editor.

LinkedIn

Bootloaders in Limbo - Between Platform Initialization and Operating System

While hardware platforms have evolved over the years, operating systems had to follow along. At the same time, their portability poses an increasing challenge in terms of complexity: A memory-intense system these days relies on DRAM that needs to be kept stable, commonly performed by dedicated controllers. Those feature thousands of registers for configuration. Beyond that, the diversity of peripherals requires lots of drivers, and the OS still has to come from somewhere. This is solved in a multi-step manner, a process refered to as "booting". However, those steps may overcomplicate the issue, bringing duplication and hard to understand interwoven components into the concept. In this talk, we will look at a range of projects involved, classify them, discuss and compare the various approaches, and come to a modern solution taming a good portion of the problem space.

Thursday, June 1st 2023 |  (Presentation | Recording)

Prasanna Thandapani

12 years of experience at Cognizant Technology Solutions in the UK, joined IIT Madras a year ago to work on the development of the Shakti RISC-V processor. 

LinkedIn

Ali Tariq

Bachelor of Science degree in Electrical Engineering from the University of Engineering and Technology Lahore, Pakistan, working as an SoC Hardware Engineer at 10xEngineers focusing on CI.

LinkedIn

RISC-V Development Labs
IIT Madras and Cloud-V

Join us for a presentation to learn more about the plan to establish a physical lab at IIT Madras, aimed at attracting and providing resources for RISC-V enthusiasts worldwide. Also, you learn about Cloud-V, an online platform that allows software developers to build, run, and test their applications on RISC-V architecture using remote hardware or emulation.

Thursday, May 11th 2023 | (Recording)

Marc Karasek

Innovative Engineering Leader: Analytical, Adaptable, Skilled Mentor, with a Proven Track Record in Software Development, Open Source Contributions, Patents, and Industry Recognition.

LinkedIn

Using Template Repo  to setup/run RISC-V Arch Test Suite under RHEL/Ubuntu

Why the need for this Template Repo?

1.        Dependencies needed to install under are split between those that need to be installed using root privileges and those that are installed into a users local home directory, under .local.

2.        Users of the arch test suite did not have the experience in installing packages, building libraries, etc.  A way to help them to get up and running was needed.

3.        Running under RHEL 8 has it’s own unique challenges.  For example Z3 a dependency for sail was not available as a package under RHEL.  So this has to be built from scratch and installed to a users local dir.  Another example was opam,  RHEL does not have this available.  Since compiling this was not an option, the binary release was chosen and is copied to  ~./local/bin/ (version being used is opam-2.1.0-x86_64-linux).

Ubuntu vs RHEL why two OSes?

While Ubuntu is by far the choice for most software developers these days.  Anyone doing chip level development is limited to what is supported by the major tool vendors, Synopsis, Cadence, Mentor, etc..

See : https://www.cadence.com/en_US/home/support/computing-platform-support.html

Thursday, April 13th 2023 |  (Presentation | Recording)

Guido Araújo

Guido Araújo is a Full Professor of Computer Science and Engineering with University of Campinas, Brazil.

LinkedIn

Using Vectorization and Matrix Multiplication Extensions to Speed-up Convolution

Convolution is one of the most computationally intensive operations in CNN. A traditional approach to computing convolutions is known as the Im2col + BLAS method. This presentation talks about SConv: a direct-convolution algorithm based on an MLIR/LLVM code-generation toolchain that uses Vectorization and Matrix Multiplication ISA extensions to improve convolution performance, surpassing Img2col + BLAS on Intel x86 and IBM POWER10. We also describe a vector-based convolution packing routine that reduces total packing time, on full model inference, of 2.0x -- 3.9x on Intel x86 and 3.6x -- 7.2x on IBM POWER10. SConv convolution speedup, over an Im2col + BLAS method based on current BLAS implementations, is 12% -- 27% on Intel x86 and 26% -- 46% on IBM POWER10. The final speed-up for end-to-end machine-learning model inference ranges from 9% -- 25% for Intel x86 and 10% -- 42% for IBM POWER10 architectures. At the end of the talk, we lay out a plan to port SConv for RISC-V architectures.

Thursday, March 16th 2023 |   (Presentation | Recording)

Bill McSpadden

RISC-V Sail model contributor and maintainer.

LinkedIn

How to add an extension to RISC-V Sail Model

New ISA features are being regularly added to the RISC-V architecture. This includes extensions that are defined by RISC-V working groups. These ratified extensions must be supported by the RISC-V Sail model. This presentation will walk listeners through the various pieces of code that are required for these new ISA features. An example, custom extension will be used to drive the discussion.

Thursday, March 2nd 2023 |  (Presentation | Recording | Sail Cookbook)

Robert Chyla

Involved in high-end debug and trace tools for 25+ years. Chair of Nexus Trace TG.

LinkedIn

N-Trace for RISC-V explained

N-Trace (Nexus IEEE 5001 based trace) is approaching ratification and will provide yet another tool to advance the adoption of the RISC-V architecture. This presentation on N-Trace will explain the requirement and discuss key N-Trace features like control, compression and trace streaming used to address the ecosystem debugging, verification and performance measurement requirements.

Thursday, February 2nd 2023 (Presentation | Recording)