Date and time: Saturday June 18th Morning

Location: Sheraton New York Times Square Hotel, New York City. More information

If any remote participant would like to join, please email the organizers for the zoom link

Welcome to SGCAR! This workshop aims to bring together experts on computing architectures using digital (i.e., not quantum) superconducting computing. Digital superconducting computing today is predominantly based on Josephson junctions (JJs), devices that are fundamentally different than CMOS transistors. In addition, information is propagated in pulses that last a few picoseconds and have a voltage of a few mVs, also a stark contrast to voltage-level encoding that we are used to in binary computing. Also, today's JJ device density limits the number of JJs per chip to a few tens of thousands, creating important area constraints and limitations in on-chip memory. On the other hand, superconducting digital computing that is predominantly based on the RSFQ variant today, is capable of operating at tens of hundreds of GHz, thus making it a candidate to preserve performance scaling in the long run.

The combination of these factors creates a research field that challenges a series of CMOS assumptions and thus is ripe with opportunities. In recent years there have been novel computing architectures that use data representation and logic gates that are entirely different from AND, OR, and the other usual suspects of binary encoding.

The goal of this workshop is to showcase recent advancements in novel and exciting compute architectures in superconducting computing in a language that is more natural to the underlying presentation the technology uses. As such, we would like to invite the computer architecture community to consider contributing to this fast-developing and promising field.

To attend, please register for ISCA and include workshops in your registration.

Further Information about Talks:

SMART: A Heterogeneous Scratchpad Memory Architecture for Superconductor SFQ-based Systolic CNN Accelerators

Abstract: Ultra-fast & low-power superconductor single-flux-quantum (SFQ)-based CNN systolic accelerators are built to enhance the CNN inference throughput. However, shift-register (SHIFT)-based scratchpad memory (SPM) arrays prevent a SFQ CNN accelerator from exceeding 40% of its peak throughput, due to the lack of random access capability. This talk first documents our study of a variety of cryogenic memory technologies, including Vortex Transition Memory (VTM), Josephson-CMOS SRAM, MRAM, and Superconducting Nanowire Memory, during which we found that none of the aforementioned technologies made a SFQ CNN accelerator achieve high throughput, small area, and low power simultaneously. Second, we present a heterogeneous SPM architecture, SMART, composed of SHIFT arrays and a random access array to improve the inference throughput of a SFQ CNN systolic accelerator. Third, we propose a fast, low-power and dense pipelined random access CMOS-SFQ array by building SFQ passive-transmission-line-based H-Trees that connect CMOS sub-banks. Finally, we create an ILP-based compiler to deploy CNN models on SMART. Experimental results show that, with the same chip area overhead, compared to the latest SHIFT-based SFQ CNN accelerator, SMART improves the inference throughput by 3.9× (2.2×), and reduces the inference energy by 86% (71%) when inferring a single image (a batch of images).

Bio: Farzaneh Zokaee is a Ph.D. candidate in the Intelligent System Engineering department at Indiana University Bloomington. The focus of her research is on designing bio-specific hardware accelerators using emerging technologies such as, resistive random-access memory (ReRAM), superconductors, and photonics. The results of her research have been published in top conferences such as MICRO, HPCA, PACT, DAC, DATE, and CAL. Additionally, she interned at Western Digital Corp., where she contributed to the development of transformer models for DNA language in the genome.

A Case for Superconducting Accelerators

Abstract: As the scaling of conventional CMOS-based technologies slows down, there is growing interest in alternative technologies that can improve performance or energy-efficiency. Superconducting circuits based on Josephson Junction (JJ) is an emerging technology that can provide devices which can be switched with pico-second latencies and consuming two orders of magnitude lower switching energy compared to CMOS. While JJ-based circuits can provide high operating frequency and energy-efficiency, this technology faces three critical challenges: limited device density and lack of area-efficient technology for memory structures, reduced gate fanout compared to CMOS, and new failure modes of Flux-Traps that occurs due to the operating environment. The lack of dense memory technology restricts the use of superconducting technology in the near term to application domains that have high compute intensity but require negligible amount of memory. In this paper, we study the use of superconducting technology to build an accelerator for SHA-256 engines commonly used in Bitcoin mining applications. We show that merely porting existing CMOS-based accelerator to superconducting technology provides 10.6X improvement in energy efficiency. Redesigning the accelerator to suit the unique constraints of superconducting technology (such as low fanout) improves the energy efficiency to 12.2X. We also investigate solutions to make the accelerator tolerant of new fault modes and show how this fault-tolerant design can be leveraged to reduce the operating current, thereby increasing the overall energy-efficiency to 46X compared to CMOS. Our paper also develops a workflow for evaluating area, performance, and power for accelerators built in superconducting technology, and this workflow can help other researchers explore designs using this technology.

Bio: Poulami Das is a PhD candidate in the School of ECE at Georgia Tech advised by Prof. Moin Qureshi. My research focuses on improving the reliability of quantum computers. I also have interests in traditional computer architecture, memory systems, and emerging technologies. I am a recipient of the Microsoft Research PhD Fellowship. Prior to joining Georgia Tech, I obtained my MS degree from UT Austin and worked as a Design Engineer at NXP.

qPALACE: A Suite of EDA Tools for Synthesis and Physical Design Optimization of Single Flux Quantum Logic Circuits

Abstract: The success of CMOS has overshadowed nearly all other solid-state device innovations over recent decades. With fundamental CMOS scaling limits close in sight, time is now ripe for exploring disruptive post-CMOS computing technologies including superconductor electronics which can deliver ultra-high performance and energy efficiency at scale. In my talk I will introduce a suite of computer aided design technologies and tools that help automate the design and optimization of superconducting single flux quantum (SFQ) logic circuits. Special emphasis will be placed on the differences between CMOS and SFQ-based solutions and benchmarking the performance and energy efficiency gains of the SFQ circuits compared to CMOS.

Bio: Massoud Pedram is currently the Charles Lee Powell Professor of Electrical Engineering and Computer Science in the USC Viterbi School of Engineering. Dr. Pedram is a recipient of the IEEE Circuits and Systems Society Charles A. Desoer Technical Achievement Award (2015), the Presidential Early Career Award for Scientists and Engineers (1996), and the National Science Foundation's Young Investigator Award (1994). Dr. Pedram was recognized as one of the four DAC Prolific Authors (with 50+ papers) and the DAC Bronze Cited Author at the 50th anniversary of the Design Automation Conf., Austin, TX (2013), received a Frequent Author Award (Top Three Author Award) at the 20th Anniversary Asia and South Pacific Design Automation Conference, Chiba/Tokyo, Japan (2015), and listed as the Second Most Prolific and Second Most Cited Author at the 20th Anniversary Int’l Symp. on Low Power Electronics and Design, Rome, Italy (2015).

The Road to Superconductor Computing with SFQ Devices

Abstract: Moore’s Law, doubling the number of transistors in a chip every two years, has so far contributed to the evolution of computer systems. Unfortunately, we cannot expect sustainable transistor shrinking anymore, marking the beginning of the so-called post-Moore era. Therefore, it has become essential to explore emerging devices, and superconductor single-flux-quantum (SFQ) logic that operates in a 4.2-kelvin environment is a promising candidate. This talk shares the “15 years history” of our SFQ architecture research with successes (and failures!) of real chip designs, e.g., revisiting microarchitecture, demonstrating over 30 GHz microprocessor, and AI accelerator designs. Then, we would like to discuss the near- and long-term challenges of superconductor computing.

Bio: Koji Inoue is a professor in the Department of Advanced Information Technology at Kyushu University, Japan. His broader research interests are computer architecture, IoT platforms, and cyber-physical systems. Currently, his driving researches target emerging devices for superconductor computing, nanophotonic computing, and quantum computing. He served as a general chair of many conferences, including the IEEE/ACM International Symposium on Microarchitecture (MICRO) 2018, the International Forum on Embedded MPSoC and Multicore (MPSoC) 2011, and the International Symposium on Low Power Electronics and Design (ISLPED) 2011. He received his Ph.D. in Computer Science and Communication Engineering from Kyushu University in 2001. He also joined Halo LSI Design & Technology, Inc., NY, as a circuit designer in 1999.

Superconductor Computing: A Possible Future

Abstract: Computing using superconductor electronics has been under development since the 1950s, yet has repeatedly lost out to other technologies except for a few niche applications. Current needs for much more energy-efficient computing, for quantum computing, and for neuromorphic computing have provided new opportunities to address larger applications. Significant improvements will be required for superconductor electronics to meet the needs, especially in circuit density and complexity. Key to improvement are innovations in superconductor devices and logic families. Technology roadmaps are under development to provide goals and timelines.

Bio: Presenter: D. Scott Holmes Affiliation: IEEE International Roadmap for Devices and Systems (IRDS).

Circuit Abstractions for Low-Cost Fan-Out

Abstract: While superconductor electronics (SCE) promise computer systems with orders of magnitude higher speeds and lower energy consumption than their complementary metal-oxide semiconductor (CMOS) counterpart, the scalability and area utilization of superconducting systems are major concerns. Some of these concerns come from device-level challenges and the gap between SCE and CMOS technology nodes, and others come from the way Josephson Junctions (JJs) are used. JJ utility can be improved with changes to the logic scheme, which greatly affects the architecture. Interestingly, though, a considerable fraction of hardware resources are still not involved in logic operations, but rather are used for fan-out and buffering purposes. This talk will describe and discuss a way to reduce these overheads through the repurposing of buffer JJs for fan-out, and a set of rules to discretize critical currents in a way that is conducive to this reassignment. Detailed analog simulations and modeling analyses indicate that this method leads to a 46% savings in the JJ count in a tree with a fan-out of 1000, as well as an average of 43.5% of the JJ count for splitting for ISCAS’85 benchmarks.

Bio: Jennifer Volk is a third-year PhD student in the Electrical and Computer Engineering department at the University of California, Santa Barbara. She is also a Student Technical Assistant at the Massachusetts Institute of Technology - Lincoln Laboratory. Her research focuses on exploiting device- and circuit-level quirks in superconductor electronics to provide benefits at the architecture and system levels. She has co-authored publications in top conferences, and her work has been awarded an IEEE Micro Top Pick and a Top Pick Honorable Mention.

Non-conventional Computing Paradigms for Area Efficient Superconducting Accelerators

Abstract: Superconducting computing potential is hindered by the low device density imposed by current technology limitations. Non-conventional computing paradigms might hold the key to address this challenge. In particular, we introduce a unary superconducting architecture (U-SFQ), based on two alternative data representations: pulse streams and race logic (RL). We propose novel building blocks including memory elements, multipliers and adders. With these building blocks we evaluate hardware accelerators in superconducting technology such as a Processing Element (PE) array, a Dot Product Unit (DPU) and a programmable Finite Impulse Response (FIR) filter. Our U-SFQ computing elements enable 28\%-96\% savings in area for the same throughput, yet, we expose the need for efficient memory elements to fully leverage the advantages of a U-SFQ architecture.

Bio: Patricia received her Ph.D. (2019) and M.Sc. (2015) from the University of Virginia, Charlottesville, VA, USA; and her Bachelors Degree from the Pontifical Xavierian University (2008), Bogota, Colombia. She also worked as an ASIC Design and Verification Engineer in Hewlett-Packard, Costa Rica. Her research interests include ultra-low power digital and mixed-signal design in CMOS and superconductors. Her work focuses on non-conventional computing paradigms to reduce power and energy consumption, such as, synchronous and asynchronous stochastic computing, computing with sigma-delta streams and race logic.

Organizers