Neel Gala

CTO| Co-Founder @ InCore Semiconductors Pvt. Ltd.

About Me:

I am currently playing the role of a CTO (Chief Technology Officer) at InCore Semiconductors Pvt. Ltd. which was Co-Founded by me in 2018.

I received my Bachelors degree (B-Tech) from the National Institute of Technology Warangal (NITW) in Electronics and Communication Engineering in year 2010. In the last quarter of 2010, I joined IIT-Madras as a project associate for a period of 18 months. During this period I was working on the design and development of some of the indigenous processors and micro-controllers which was partially funded by multiple Indian Defense agencies. By January 2012, I joined the Computer Science and Engineering Department at IIT-Madras (IITM) as a Direct PhD Candidate with Prof. V. Kamakoti as my advisor. I was also the recipient of the TCS-PHD fellowship for 2 consecutive years. I received my PhD Degree in the last quarter of 2016 have published more than 16 international articles and papers. Since then I have been leading the technical team of the SHAKTI Processor Systems and have recently co-founded InCore Semiconductors Pvt. Ltd. as well.

Contact Info:

Email: neelgala [at] gmail [dot] com

LinkedIn Profile

About InCore Semiconductors :

InCore is India's leading provider of silicon proven RISC-V processor and SoC IP. We also provide specialised cores aimed at fault tolerant, security and AI/ML verticals. InCore's partner network offers the full range of services needed to transition from concept to high volume manufacturing of ASIC parts and boards. We have partnerships with leading foundries allowing us to support our customers on multiple process nodes.


  • PhD in CSE Dept @ IIT Madras [2012-2016]
  • BTech in ECE Dept @ NIT Warangal [2006-2010]


  1. Vinod Ganesan, Sanchari Sen, Pratyush Kumar, Neel Gala, Kamakoti Veezhinathan, and Anand Raghunathan, "Sparsity-Aware Caches to Accelerate Deep Neural Networks", in Design, Automation and Test in Europe (DATE) Conference, 2020.
  2. Sugandha Tiwari, Neel Gala, Chester Rebeiro, V. Kamakoti, PERI: A Posit Enabled RISC-V Core. CoRR abs/1908.01466 (2019)
  3. S. Murugan and N. Gala, "ELENA: A low-cost portable electronic nose for alcohol characterisation," 2017 IEEE SENSORS, Glasgow, 2017, pp. 1-3. doi: 0.1109/ICSENS.2017.8234218
  4. Arjun Menon, Subadra Murugan, Chester Rebeiro, Neel Gala, and Kamakoti Veezhinathan. 2017. "Shakti-T: A RISC-V Processor with Light Weight Security Extensions". In Proceedings of the Hardware and Architectural Support for Security and Privacy (HASP '17). ACM, New York, NY, USA, Article 2, 8 pages. DOI:
  5. A. Roy, S. Venkataramani, N. Gala, S. Sen, K. Veezhinathan and A. Raghunathan, "A Programmable Event-driven Architecture for Evaluating Spiking Neural Networks," 2017 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED), Taipei, 2017, pp. 1-6. doi: 10.1109/ISLPED.2017.8009176
  6. Neel Gala, Sarada Krithivasan, Wei-Yu Tsai, Xueqing Li, Vijaykrishnan N. V. Kamakoti, “An Accuracy Tunable Non-Boolean Co-processor using Coupled Nano-oscillators”, accepted in ACM Journal of Emerging Technologies in Computing (JETC), April, 2017.
  7. Neel Gala, Swagath Venkatramani, Anand Raghunathan, V. Kamakoti, “Approximate Error Detection with Stochastic Checkers”, accepted in IEEE Transactions in VLSI (TVLSI), March, 2017.
  8. Neel Gala, Arjun Menon, Rahul Bodduna, G. S. Madhusudan, V. Kamakoti, “SHAKTI Processors: An Open-Source Hardware Initiative”, IEEE International conference on VLSID, 2016.
  9. Neel Gala, Swagath Venkatramani, Anand Raghunathan, V. Kamakoti, “STOCK: Stochastic Checkers for low-overhead error detection”,accepted, ISLPED, 2016.
  10. Neel Gala, Swagath Venkatramani, Anand Raghunathan, V. Kamakoti, “STOCK: Stochastic Checkers for faults in Approximate Applications”, Work-in-Progress, DAC 2016.
  11. Arnab Roy, Neel Gala, V. Kamakoti, Swagath Venkatramani, Anand Raghunathan, “Event-Driven Processing Architecture for Neuromorphic Computing”, poster at Workshop on Computational Brain Research, IIT-Madras, 2016
  12. Swagath Venkataramani, Anand Raghunathan, Neel Gala, Sanjay Ganapathy, Balaraman Ravindran , V. Kamakoti, “Stochastic Computing : Information Processing with Bitstreams”, poster at Workshop on Computational Brain Research, IIT-Madras, 2016
  13. Vikas Chauhan, Neel Gala and V. Kamakoti, “ChADD: An ADD based Chisel Compiler with reduced Syntactic Variance”, VLSI Design ,IEEE, 2016.
  14. Sukrat Gupta, Neel Gala, G. S. Madhusudan and V. Kamakoti, “SHAKTI-F : A Fault Tolerant Microprocessor Architecture.”, Asian Test Symposium, IEEE, 2015.
  15. Neel Gala, V. R. Devanathan, V. Visvanathan and V. Kamakoti “Best is the Enemy of Good: Design Techniques for Low Power Tunable Approximate Application Specific Integrated Chips Targeting Media-Based Applications ”, Journal of Low Power Electronics, June 2015
  16. Neel Gala, V. R. Devanathan, K. Srinivasan, V. Visvanathan, and V. Kamakoti, “ProCA: Progressive Configuration Aware Design Methodology for Low Power Stochastic ASICs”, in the Proceedings of the 27 th International Conference on VLSI Design, .pp 342-347, 2014.
  17. Nihar Rathod, Shankar Balachandran, Neel Gala, “CAERUS: an effective arbitration and ejection policy for routing in an unidirectional torus”, in the Proceedings of the 8th International Workshop on Interconnection Network Architecture: On-Chip, Multi-Chip, 2014
  18. Neel Gala, V. R. Devanathan, V. Visvanathan, V. Gandhi and V. Kamakoti, ”Tunable stochastic computing using layered synthesis and temperature adaptive voltage scaling”, in the Proceedings of the 5 th Asian Symposium on Quality Electronic Design (ASQED),.pp 103-112, 2013.


Reconfiguring an ASIC at runtime

Patent number: 9698779

Abstract: Methods for reconfiguring an ASIC at runtime without using voltage over scaling. A functional criticality of a set of logic in the ASIC is identified. Then, the set of logic are classified into a set of regions based on the functional criticality, each region of the set of regions having a target error threshold. Further, each region is power gated at runtime based on the functional criticality such that the target error threshold is achieved without using voltage over scaling.

Type: Grant

Filed: October 3, 2014

Date of Patent: July 4, 2017


Inventors: Devanathan Varadarajan, Karthik Srinivasan, Neel Talakshi Gala


CTO @ InCore Semiconductors Pvt. Ltd. [May 2018-present]

I have also co-founded the company along with Mr. G. S. Madhusudan, Arjun Menon, Rahul Bodduna and Vinod Ganesan


Project Officer @ IIT Madras [Aug 2016- April 2018]

I was the technical lead for the SHAKTI Processor Systems project at IIT-Madras. I was also amongst the initial members who kick-started this project back in 2013. Since 2013 to 2016, during my PhD tenure, I was associated with the project in a student's capacity. As part of this project, I helped defined the micro-architecture of the E, C and I Class processors. I also contributed in building the first SoC which consisted of multiple peripherals like I2C, QSPI, DMA, SDRAM, UART, etc. All these IPs were home-grown and available in open-source under BSD license. In the first quarter of 2018, I also headed the effort of the first silicon tapeout of the SHAKTI C-class processor. This was a test chip done at Intel's 22FFL technology node.


Intern @ Texas Instruments India Ltd. [Feb-Aug 2013]

During my internship, I was given a chance to work on various problems related to “Stochastic and Approximate Computing Designs“ under the mentorship of Dr. V. Devanathan. My initial work dealt with approximating an open-core H.264 video decoder such that we gain graceful degradation in quality with significant power savings. I then proceeded to work on a GPU class of applications and hardware. The details of the work can be found in the published papers. I also had a chance to work on some of TI’s imaging IP. The internship gave me huge exposure to the industry standards, tools and software.


Project Associate @ RISE Lab, IITM [Aug 2010 - Jan 2012]

Worked on the development of a complete indigenous super-scalar 32-bit RISC micro-processor for the DRDO using Bluespec System Verilog. The the ISA was provided by DRDO, the micro-architecture on the other hand was design in-house at RISE LAB. My contribution was developing the complete code skeleton from scratch including MMU, reservation stations, execution units, etc. This processor is under verification stage.

Along side, a minimized version of the same processor (with lesser ISA support) was integrated with various peripherals such as SPI, I2C, etc to build a hardware secure SoC. This SoC is currently under prototyping phase.


Intern @ RISE Lab, IITM [May-Jun 2009]

The project involved understanding the efficiency of a new HDL- Bluespec System Verilog (BSV) in equivalence checking. The DUT was a Stand Alone Finite Impulse Test (SAFIT) unit. Idea was to leverage the automated control logic solution of BSV and verify the quality of the design and its efficiency in terms of ease of design and ability to meet the final requirements. This excersize gave me exposure to some of the important industrial tools such as Formal-Pro, Modelsim, VCS etc.


Intern @ Bhabha Atomic Research Centre [May-July 2008]

This project was undertaken at the end of my 2nd year of undergraduate studies at BARC. The work involved designing a Test-bench in VHDL for the verification of hardware circuits such as Scalar-Timer and Ramp Generator which were targeted for a Prototype Fast Breeder Reactor. The final test-bench was burned into the on-board Actel FPGA using Libero. The working of the entire system was then verified on a real-time digital oscilloscope by probing various inputs/outputs of the system. The project introduced me digital design, HDLs and hardware design.


Technical Skills

  • Bluespec System Verilog
  • Verilog/VHDL
  • Python
  • Conversant with a variety of FrontEnd and BackEnd VLSI tools such as: Design Compiler, RTL Compiler, LEC, Formalpro, Modelsim, VCS, etc.
  • Conversant with FPGA emulation platforms offered by Xilinx, Altera and MicroSemi.
  • Latex.