European Network of Excellence on High Performance and Embedded
Architecture and Compilation (HiPEAC)
Embedded Files
Aim:
Area and Power efficient Hardware chip design and implementation of Neuromorfic Computing Accelerator using Emerging Reconfigurable nanotechnologies
Objectives
Design and Implement Configurable architecture that can configure to different activation function computation using the same logic resources
Explore the Semi-custom ASIC Design approach for the efficient design of Complex VLSI Circuits
Design an area and power efficient Neuron Architecture for Semi-custom ASIC design Approach.
Exploration of different computation of neural network on same hardware resources for the application where the area and power are in tight budget such as Edge AI and AI Enable IoT.
Duration of the Project: 3 Months (October 2019 - January 2020) Project Cost: INR 4,39,649/-
Funding Agency
European FP7 ICT Cooperation program
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