【VHDL記述】

library IEEE;

use IEEE.std_logic_1164.all;

use IEEE.std_logic_unsigned.all;

entity COUNTER_4 is

port( CK, RESET, X : in std_logic;

Y : out std_logic );

end COUNTER_4;

architecture BEHAVIOR of COUNTER_4 is

signal COUNT : std_logic_vector(1 downto 0);

begin

Y <= COUNT(0) and COUNT(1);

process( RESET, CK ) begin

if ( RESET = '1' ) then

COUNT <= "00";

elsif ( CK'event and CK = '0' ) then

if ( X = '1' ) then

if ( COUNT = "11" ) then

COUNT <= "00";

else

COUNT <= COUNT + "01";

end if;

end if;

end if;

end process;

end BEHAVIOR;

【Verilog-HDL記述】

module COUNTER_4 (

CK, RESET, X,

Y

);

input CK, RESET, X;

output Y;

reg[ 1 : 0 ] COUNT;

assign Y = & COUNT;

always @ ( negedge CK or posedge RESET ) begin

if ( RESET ) begin

COUNT <= 2'b00;

end else if ( X ) begin

COUNT <= COUNT + 2'b01;

end

end

endmodule