4進カウンタ(ステートマシンとして記述)
掲載ページ:135、リスト番号:6.1
【VHDL記述】
library IEEE;
use IEEE.std_logic_1164.all;
entity COUNTER_4 is
port( CK, RESET, X : in std_logic;
Y : out std_logic );
end COUNTER_4;
architecture STATE_MACHINE of COUNTER_4 is
type STATE is ( Q0, Q1, Q2, Q3 );
signal CURRENT_STATE, NEXT_STATE : STATE;
begin
STORAGE : process ( RESET, CK ) begin
if ( RESET = '1' ) then
CURRENT_STATE <= Q0;
elsif ( CK'event and CK = '0' ) then
CURRENT_STATE <= NEXT_STATE;
end if;
end process;
COMB : process ( CURRENT_STATE, X ) begin
case CURRENT_STATE is
when Q0 => if ( X = '1' ) then
NEXT_STATE <= Q1; Y <= '0';
else
NEXT_STATE <= Q0; Y <= '0';
end if;
when Q1 => if ( X = '1' ) then
NEXT_STATE <= Q2; Y <= '0';
else
NEXT_STATE <= Q1; Y <= '0';
end if;
when Q2 => if ( X = '1' ) then
NEXT_STATE <= Q3; Y <= '0';
else
NEXT_STATE <= Q2; Y <= '0';
end if;
when Q3 => if ( X = '1' ) then
NEXT_STATE <= Q0; Y <= '1';
else
NEXT_STATE <= Q3; Y <= '0';
end if;
end case;
end process;
end STATE_MACHINE;
【Verilog-HDL記述】
module COUNTER_4 (
CK, RESET, X,
Y
);
input CK, RESET, X;
output Y;
parameter Q0 = 2'b00, Q1 = 2'b01, Q2 = 2'b10, Q3 = 2'b11;
reg[ 1 : 0 ] CURRENT_STATE;
wire[ 1 : 0 ] NEXT_STATE;
always @ ( negedge CK or posedge RESET ) begin
if ( RESET ) begin
CURRENT_STATE <= Q0;
end else begin
CURRENT_STATE <= NEXT_STATE;
end
end
assign NEXT_STATE = FUNC_NS( CURRENT_STATE, X );
assign Y = (( CURRENT_STATE == Q3 ) & X ) ? 1'b1 : 1'b0;
function[ 1 : 0 ] FUNC_NS;
input[ 1 : 0 ] CURRENT_STATE;
input X;
begin
case ( CURRENT_STATE )
Q0: FUNC_NS = X ? Q1 : Q0;
Q1: FUNC_NS = X ? Q2 : Q1;
Q2: FUNC_NS = X ? Q3 : Q2;
default: FUNC_NS = X ? Q0 : Q3;
endcase
end
endfunction
endmodule
【合成結果】