【VHDL記述】

library IEEE;

use IEEE.std_logic_1164.all;

use IEEE.std_logic_unsigned.all;

entity COUNTER_N is

generic( F : integer := 4; -- FFの数

N : integer := 10 ); -- N進カウンタ(ただし，N =< 2**F )

port( CK, RESET : in std_logic;

Y : out std_logic_vector(F-1 downto 0));

end COUNTER_N;

architecture BEHAVIOR of COUNTER_N is

signal COUNT : std_logic_vector(F-1 downto 0);

begin

process( RESET, CK ) begin

if ( RESET = '1' ) then

COUNT <= (others => '0');

elsif ( CK'event and CK = '1' ) then

if ( COUNT = N-1 ) then

COUNT <= (others => '0');

else

COUNT <= COUNT + 1;

end if;

end if;

end process;

Y <= COUNT;

end BEHAVIOR;

【Verilog-HDL記述】

module COUNTER_N (

CK, RESET,

Y

);

parameter F = 4; // FFの数

parameter N = 10; // N進カウンタ(ただし，N =< 2**F )

input CK, RESET;

output[ F-1 : 0 ] Y;

reg[ F-1 : 0 ] COUNT;

always @ ( negedge CK or posedge RESET ) begin

if ( RESET ) begin

COUNT <= 0;

end else if ( COUNT == N-1 ) begin

COUNT <= 0;

end else begin

COUNT <= COUNT + 1;

end

end

assign Y = COUNT;

endmodule