【VHDL記述】

library IEEE;

use IEEE.std_logic_1164.all;

entity SYNC_RS_FF is

port( CK, R, S : in std_logic;

Q, Qnot : out std_logic );

end SYNC_RS_FF;

architecture STRUCTURE of SYNC_RS_FF is

component RS_FF

port ( R, S : in std_logic;

Q, Qnot : out std_logic );

end component;

signal SR, SS : std_logic;

begin

SR <= R and CK;

SS <= S and CK;

COMP : RS_FF port map ( SR, SS, Q, Qnot );

end STRUCTURE;

【Verilog-HDL記述】

module SYNC_RS_FF (

CK, R, S,

Q, Qnot

);

input CK, R, S;

output Q, Qnot;

wire SR, SS;

assign SR = R & CK;

assign SS = S & CK;

RS_FF COMP ( SR, SS, Q, Qnot );

endmodule