【VHDL記述】

entity HALF_ADDER is

port ( A, B : in bit;

S, C : out bit );

end HALF_ADDER;

architecture STRUCTURE of HALF_ADDER is

begin

S <= A xor B;

C <= A and B;

end STRUCTURE;

【Verilog-HDL記述】

module HALF_ADDER (

A, B,

S, C

);

input A, B;

output S, C;

assign S = A ^ B;

assign C = A & B;

endmodule