【VHDL記述】

library IEEE;

use IEEE.std_logic_1164.all;

entity FULL_ADDER is

port ( A, B, CIN : in std_logic;

SUM, COUT : out std_logic );

end FULL_ADDER;

architecture STRUCTURE of FULL_ADDER is

-- HALF_ADDERのコンポーネント宣言

component HALF_ADDER

port ( A, B : in std_logic;

S, C : out std_logic );

end component;

signal C1_C, C1_S, C2_C : std_logic;

begin

-- コンポーネント・インスタンス文

COMP1 : HALF_ADDER port map ( A, B, C1_S, C1_C );

COMP2 : HALF_ADDER port map ( C1_S, CIN, SUM, C2_C );

COUT <= C1_C or C2_C;

end STRUCTURE;

【Verilog-HDL記述】

module FULL_ADDER (

A, B, CIN,

SUM, COUT

);

input A, B, CIN;

output SUM, COUT;

wire C1_C, C1_S, C2_C;

// モジュール呼び出し

HALF_ADDER COMP1 ( A, B, C1_S, C1_C );

HALF_ADDER COMP2 ( C1_S, CIN, SUM, C2_C );

assign COUT = C1_C | C2_C;

endmodule