Embedded Files
【VHDL記述】
library IEEE;
use IEEE.std_logic_1164.all;
entity FA_CARRY is
port ( A, B, C : in std_logic;
CO : out std_logic );
end FA_CARRY;
architecture TRUTH_TABLE of FA_CARRY is
signal INDATA : std_logic_vector(2 downto 0);
begin
INDATA <= A & B & C;
process (INDATA) begin
if (INDATA = "000") then
CO <= '0';
elsif (INDATA = "001") then
CO <= '0';
elsif (INDATA = "010") then
CO <= '0';
elsif (INDATA = "011") then
CO <= '1';
elsif (INDATA = "100") then
CO <= '0';
elsif (INDATA = "101") then
CO <= '1';
elsif (INDATA = "110") then
CO <= '1';
else
CO <= '1';
end if;
end process;
end TRUTH_TABLE;
【Verilog-HDL記述】
module FA_CARRY (
A, B, C,
CO
);
input A, B, C;
output CO;
wire[ 2 : 0 ] INDATA;
assign INDATA = { A, B, C };
assign CO = FUNC_CO( INDATA );
// function定義
function FUNC_CO;
input[ 2 : 0 ] INDATA;
begin
if ( INDATA == 3'b000 ) begin
FUNC_CO = 1'b0;
end else if ( INDATA == 3'b001 ) begin
FUNC_CO = 1'b0;
end else if ( INDATA == 3'b010 ) begin
FUNC_CO = 1'b0;
end else if ( INDATA == 3'b011 ) begin
FUNC_CO = 1'b1;
end else if ( INDATA == 3'b100 ) begin
FUNC_CO = 1'b0;
end else if ( INDATA == 3'b101 ) begin
FUNC_CO = 1'b1;
end else if ( INDATA == 3'b110 ) begin
FUNC_CO = 1'b1;
end else begin
FUNC_CO = 1'b1;
end
end
endfunction
endmodule
【合成結果】
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