【VHDL記述】

library IEEE;

use IEEE.std_logic_1164.all;

entity DECODER_2_4 is

port ( D : in std_logic_vector(1 downto 0);

Y : out std_logic_vector(3 downto 0));

end DECODER_2_4;

architecture DATAFLOW of DECODER_2_4 is

begin

process ( D )

begin

-- case文による出力の場合分け

case D is

when "00" => Y <= "0001";

when "01" => Y <= "0010";

when "10" => Y <= "0100";

when "11" => Y <= "1000";

when others => Y <= "XXXX";

end case;

end process;

end DATAFLOW;

【Verilog-HDL記述】

module DECODER_2_4 (

D,

Y

);

input[ 1 : 0 ] D;

output[ 3 : 0 ] Y;

assign Y = FUNC_Y( D );

// function定義

function[ 3 : 0 ] FUNC_Y;

input[ 1 : 0 ] D;

begin

// case文による出力の場合分け

case ( D )

2'b00 : FUNC_Y = 4'b0001;

2'b01 : FUNC_Y = 4'b0010;

2'b10 : FUNC_Y = 4'b0100;

2'b11 : FUNC_Y = 4'b1000;

default : FUNC_Y = 4'bxxxx;

endcase

end

endfunction

endmodule