【VHDL記述】

library IEEE;

use IEEE.std_logic_1164.all;

entity ENCODER_4_2 is

port ( D : in std_logic_vector(3 downto 0);

Y : out std_logic_vector(1 downto 0));

end ENCODER_4_2;

architecture DATAFLOW of ENCODER_4_2 is

begin

process ( D )

begin

-- case文による出力の場合分け

case D is

when "0001" => Y <= "00";

when "0010" => Y <= "01";

when "0100" => Y <= "10";

when "1000" => Y <= "11";

when others => Y <= "XX";

end case;

end process;

end DATAFLOW;

【Verilog-HDL記述】

module ENCODER_4_2 (

D,

Y

);

input[ 3 : 0 ] D;

output[ 1 : 0 ] Y;

assign Y = FUNC_Y( D );

// function定義

function[ 1 : 0 ] FUNC_Y;

input[ 3 : 0 ] D;

begin

// case文による出力の場合分け

case ( D )

4'b0001 : FUNC_Y = 2'b00;

4'b0010 : FUNC_Y = 2'b01;

4'b0100 : FUNC_Y = 2'b10;

4'b1000 : FUNC_Y = 2'b11;

default : FUNC_Y = 2'bxx;

endcase

end

endfunction

endmodule