【VHDL記述】

library IEEE;

use IEEE.std_logic_1164.all;

use IEEE.std_logic_unsigned.all;

entity MULTIPLIER is

generic( L : integer := 8 );

port ( CLK, RESET, START : in std_logic;

X : in std_logic_vector(L-1 downto 0);

Y : in std_logic_vector(L-1 downto 0);

Z : out std_logic_vector(2*L-1 downto 0));

end MULTIPLIER;

architecture SYNC_SEQ of MULTIPLIER is

type STATE is (INIT, OP_MUL);

signal CRST, NTST : STATE;

signal SET_MUL : std_logic;

signal S_X : std_logic_vector(2*L-2 downto 0);

signal S_Y : std_logic_vector(L-1 downto 0);

signal S_ADD, S_SEL, S_MUL : std_logic_vector(2*L-1 downto 0);

signal C_MUL : integer range 0 to L+1;

constant ZV_X : std_logic_vector(L-2 downto 0) := (others => '0');

begin

P_CONTROL_REG: process ( CLK, RESET ) begin

if ( RESET = '1' ) then

CRST <= INIT;

elsif ( CLK'event and CLK = '1' ) then

CRST <= NTST;

end if;

end process;

P_CONTROL_CNT: process ( CLK ) begin

if ( CLK'event and CLK = '1' ) then

if (CRST = INIT) then

C_MUL <= 0;

elsif ( CRST = OP_MUL ) then

C_MUL <= C_MUL + 1;

end if;

end if;

end process;

P_CONTROL_STF: process ( CRST, C_MUL, START ) begin

case CRST is

when INIT => if ( START = '1' ) then

SET_MUL <= '1';

NTST <= OP_MUL;

else

SET_MUL <= '0';

NTST <= INIT;

end if;

when OP_MUL => SET_MUL <= '0';

if ( C_MUL = L ) then

NTST <= INIT;

else

NTST <= OP_MUL;

end if;

end case;

end process;

P_SHIFT_REG_A: process ( CLK, RESET ) begin

if ( RESET = '1' ) then

S_X <= (others => '0');

elsif ( CLK'event and CLK = '1' ) then

if ( SET_MUL = '1' ) then

S_X <= ZV_X & X;

else

S_X <= S_X(2*L-3 downto 0) & '0';

end if;

end if;

end process;

P_SHIFT_REG_B: process ( CLK, RESET ) begin

if ( RESET = '1' ) then

S_Y <= (others => '0');

elsif ( CLK'event and CLK = '1' ) then

if ( SET_MUL = '1' ) then

S_Y <= Y;

else

S_Y <= '0' & S_Y(L-1 downto 1);

end if;

end if;

end process;

P_ADDER: S_ADD <= S_MUL + ('0' & S_X);

P_SELECTOR: process ( S_Y, S_ADD, S_MUL ) begin

if ( S_Y(0) = '1' ) then

S_SEL <= S_ADD;

else

S_SEL <= S_MUL;

end if;

end process;

P_RESULT: process ( CLK, RESET ) begin

if ( RESET = '1' ) then

S_MUL <= (others => '0');

elsif ( CLK'event and CLK = '1' ) then

if (SET_MUL = '1') then

S_MUL <= (others => '0');

else

S_MUL <= S_SEL;

end if;

end if;

end process;

Z <= S_MUL;

end SYNC_SEQ;

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