Embedded Files
【VHDL記述】
-- パッケージ
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
package MUL_MOD_PACK is
constant CL : integer := 7; -- 文字コード長(Bits)
constant BS : integer := 1; -- ブロックサイズ(文字数)
constant BL : integer := CL * BS; -- ブロック長(Bits)
constant KL : integer := 7; -- 公開鍵のビット長(Bits)
constant ML : integer := 7; -- 法のビット長(Bits)
end MUL_MOD_PACK;
-- 乗算(*)＋剰余(mod)計算
-- RC = (MC * MR) mod DS
library IEEE, WORK;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use WORK.MUL_MOD_PACK.all;
entity MUL_MOD is
port (
CLK, RESET, START : in std_logic;
MC : in std_logic_vector(BL-1 downto 0); -- 被乗数
MR : in std_logic_vector(BL-1 downto 0); -- 乗数
DS : in std_logic_vector(ML-1 downto 0); -- 除数
DONE : out std_logic;
RS : out std_logic_vector(ML-1 downto 0)); -- 結果
end MUL_MOD;
architecture SYNC of MUL_MOD is
type STATE is (INIT, OP_MUL, OP_MOD);
signal CRST, NTST : STATE;
signal SET_MUL, SET_MOD : std_logic;
signal MM_DONE, S_DONE : std_logic;
signal S_MC : std_logic_vector(2*BL-2 downto 0);
signal S_MR : std_logic_vector(BL-1 downto 0);
signal S_DS1, S_RS : std_logic_vector(ML-1 downto 0);
signal S_DS2, S_MOD, S_SUB : std_logic_vector(2*BL+ML-1 downto 0);
signal S_ADD, S_SEL, S_MUL : std_logic_vector(2*BL-1 downto 0);
signal C_MUL : integer range 0 to BL+1;
signal C_MOD : integer range 0 to 2*BL+1;
constant ZV_MC : std_logic_vector(BL-2 downto 0) := (others => '0');
constant ZV_DD : std_logic_vector(ML-1 downto 0) := (others => '0');
constant ZV_DS : std_logic_vector(2*BL-2 downto 0) := (others => '0');
begin
-- 制御回路(ステートマシン)用レジスタ
P_CONTROL_REG: process (CLK, RESET)
begin
if (RESET = '1') then
CRST <= INIT;
elsif (CLK'event and CLK = '1') then
CRST <= NTST;
end if;
end process;
-- 制御回路(ステートマシン)用状態遷移回路
P_CONTROL_STF: process (CRST, C_MUL, C_MOD, START)
begin
case CRST is
when INIT => MM_DONE <= '0';
SET_MOD <= '0';
if (START = '1') then
SET_MUL <= '1';
NTST <= OP_MUL;
else
SET_MUL <= '0';
NTST <= INIT;
end if;
when OP_MUL => SET_MUL <= '0';
if (C_MUL = BL) then
SET_MOD <= '1';
NTST <= OP_MOD;
else
NTST <= OP_MUL;
end if;
when OP_MOD => SET_MOD <= '0';
if (C_MOD = 2*BL) then
MM_DONE <= '1';
NTST <= INIT;
else
NTST <= OP_MOD;
end if;
end case;
end process;
-- 制御回路(ステートマシン)用カウンタ
P_CONTROL_CNT: process (CLK)
begin
if (CLK'event and CLK = '1') then
if (CRST = INIT) then
C_MUL <= 0;
C_MOD <= 0;
elsif (CRST = OP_MUL) then
C_MUL <= C_MUL + 1;
C_MOD <= 0;
elsif (CRST = OP_MOD) then
C_MUL <= 0;
C_MOD <= C_MOD + 1;
end if;
end if;
end process;
-- 被乗数格納用シフトレジスタ
P_SHIFTER_MC: process (CLK, RESET)
begin
if (RESET = '1') then
S_MC <= (others => '0');
elsif (CLK'event and CLK = '1') then
if (SET_MUL = '1') then
S_MC <= ZV_MC & MC;
else
S_MC <= S_MC(2*BL-3 downto 0) & '0';
end if;
end if;
end process;
-- 乗数格納用シフトレジスタ
P_SHIFTER_MR: process (CLK, RESET)
begin
if (RESET = '1') then
S_MR <= (others => '0');
elsif (CLK'event and CLK = '1') then
if (SET_MUL = '1') then
S_MR <= MR;
else
S_MR <= '0' & S_MR(BL-1 downto 1);
end if;
end if;
end process;
-- 除数格納用レジスタ
P_REG_DS: process (CLK, RESET)
begin
if (RESET = '1') then
S_DS1 <= (others => '0');
elsif (CLK'event and CLK = '1') then
if (SET_MUL = '1') then
S_DS1 <= DS;
else
S_DS1 <= S_DS1;
end if;
end if;
end process;
-- 乗算部用加算器
P_ADDER: S_ADD <= S_MUL + ('0' & S_MC);
-- 乗算部用セレクタ
P_SELECTOR_MUL: process (S_MR, S_ADD, S_MUL)
begin
if (S_MR(0) = '1') then
S_SEL <= S_ADD;
else
S_SEL <= S_MUL;
end if;
end process;
-- 乗算結果格納用レジスタ
P_RESULT_MUL: process (CLK, RESET)
begin
if (RESET = '1') then
S_MUL <= (others => '0');
elsif (CLK'event and CLK = '1') then
if (SET_MUL = '1') then
S_MUL <= (others => '0');
else
S_MUL <= S_SEL;
end if;
end if;
end process;
-- 被除数格納用レジスタ
P_REG_DD: process (CLK, RESET)
begin
if (RESET = '1') then
S_MOD <= (others => '0');
elsif (CLK'event and CLK = '1') then
if (SET_MOD = '1') then
S_MOD <= ZV_DD & S_MUL;
else
S_MOD <= S_SUB;
end if;
end if;
end process;
-- 除数格納用シフトレジスタ
P_SHIFTER_DS: process (CLK, RESET)
begin
if (RESET = '1') then
S_DS2 <= (others => '0');
elsif (CLK'event and CLK = '1') then
if (SET_MOD = '1') then
S_DS2 <= '0' & S_DS1 & ZV_DS;
else
S_DS2 <= '0' & S_DS2(2*BL+ML-1 downto 1);
end if;
end if;
end process;
-- mod演算部用減算器
P_SUBTRUCTOR: process (S_DS2, S_MOD)
begin
if (S_MOD >= S_DS2) then
S_SUB <= S_MOD - S_DS2;
else
S_SUB <= S_MOD;
end if;
end process;
-- mod演算結果格納用レジスタ
P_REG_RS: process (CLK, RESET)
begin
if (RESET = '1') then
S_DONE <= '0';
S_RS <= (others => '0');
elsif (CLK'event and CLK = '1') then
if (MM_DONE = '1') then
S_DONE <= '1';
S_RS <= S_MOD(ML-1 downto 0);
elsif (SET_MUL = '1') then
S_DONE <= '0';
S_RS <= (others => '0');
else
S_DONE <= S_DONE;
S_RS <= S_RS;
end if;
end if;
end process;
RS <= S_RS;
DONE <= S_DONE;
end SYNC;
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【合成結果】
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