【VHDL記述】

library IEEE;

use IEEE.std_logic_1164.all;

entity LATCH is

port( ST, D : in std_logic;

Q, Qnot : out std_logic );

end LATCH;

architecture BEHAVIOR of LATCH is

signal TMP : std_logic;

begin

process ( ST, D ) begin

-- if文にはelse項を記述しない

if ( ST = '1' ) then

TMP <= D;

end if;

end process;

Q <= TMP;

Qnot <= not TMP;

end BEHAVIOR;

【Verilog-HDL記述】

module LATCH (

ST, D,

Q, Qnot

);

input ST, D;

output Q, Qnot;

reg TMP;

always @ ( ST or D ) begin

// if文にはelse項を記述しない

if ( ST == 1'b1 ) begin

TMP <= D;

end

end

assign Q = TMP;

assign Qnot = ~TMP;

endmodule