【VHDL記述】

library IEEE;

use IEEE.std_logic_1164.all;

entity MS_JK_FF is

port( CK, J, K : in std_logic;

Q, Qnot : out std_logic );

end MS_JK_FF;

architecture STRUCTURE of MS_JK_FF is

component JK_FF

port(

CK, J, K : in std_logic;

Q, Qnot : out std_logic);

end component;

signal SJ, SK, SC : std_logic;

begin

SC <= not CK;

COMP1 : JK_FF port map ( CK, J, K, SJ, SK );

COMP2 : JK_FF port map ( SC, SJ, SK, Q, Qnot );

end STRUCTURE;

【Verilog-HDL記述】

module MS_JK_FF (

CK, J, K,

Q, Qnot

);

input CK, J, K;

output Q, Qnot;

wire SJ, SK, SC;

assign SC = ~CK;

JK_FF COMP1 ( CK, J, K, SJ, SK );

JK_FF COMP2 ( SC, SJ, SK, Q, Qnot );

endmodule