【VHDL記述】

library IEEE;

use IEEE.std_logic_1164.all;

entity PET_D_FF is

port( CK, D : in std_logic;

Q : out std_logic );

end PET_D_FF;

architecture BEHAVIOR of PET_D_FF is

begin

process ( CK ) begin

if ( CK'event and CK = '1' ) then

Q <= D;

end if;

end process;

end BEHAVIOR;

【Verilog-HDL記述】

module PET_D_FF (

CK, D,

Q

);

input CK, D;

output Q;

reg Q;

always @ ( posedge CK ) begin

Q <= D;

end

endmodule