【VHDL記述】

library IEEE;

use IEEE.std_logic_1164.all;

-- std_logic_vector型どうしの演算を行うために使用

use IEEE.std_logic_unsigned.all;

entity ADDER4 is

port ( A, B : in std_logic_vector(3 downto 0);

S : out std_logic_vector(4 downto 0));

end ADDER4;

architecture BEHAVIOR of ADDER4 is

begin

S <= ('0' & A) + ('0' & B);

end BEHAVIOR;

【Verilog-HDL記述】

module ADDER4 (

A, B,

S

);

input[ 3 : 0 ] A, B;

output[ 4 : 0 ] S;

assign S = { 1'b0, A } + { 1'b0, B };

endmodule