【VHDL記述】

library IEEE;

use IEEE.std_logic_1164.all;

entity MULTIPLEXER4 is

port ( D : in std_logic_vector(3 downto 0);

S : in std_logic_vector(1 downto 0);

Y : out std_logic );

end MULTIPLEXER4;

architecture DATAFLOW of MULTIPLEXER4 is

begin

-- process文(順次処理文の記述)

process ( D, S )

begin

-- if文による出力の場合分け

if ( S = "00" ) then

Y <= D(0);

elsif ( S = "01" ) then

Y <= D(1);

elsif ( S = "10" ) then

Y <= D(2);

else

Y <= D(3);

end if;

end process;

end DATAFLOW;

【Verilog-HDL記述】

module MULTIPLEXER4 (

D,

S,

Y

);

input[ 3 : 0 ] D;

input[ 1 : 0 ] S;

output Y;

assign Y = FUNC_Y( D, S );

// function定義(順次処理文の記述)

function FUNC_Y;

input[ 3 : 0 ] D;

input[ 1 : 0 ] S;

begin

// if文による出力の場合分け

if ( S == 2'b00 ) begin

FUNC_Y = D[ 0 ];

end else if ( S == 2'b01 ) begin

FUNC_Y = D[ 1 ];

end else if ( S == 2'b10 ) begin

FUNC_Y = D[ 2 ];

end else begin

FUNC_Y = D[ 3 ];

end

end

endfunction

endmodule