【VHDL記述】

library IEEE;

use IEEE.std_logic_1164.all;

entity DEMULTIPLEXER4 is

port ( D : in std_logic;

S : in std_logic_vector(1 downto 0);

Y : out std_logic_vector(3 downto 0));

end DEMULTIPLEXER4;

architecture DATAFLOW of DEMULTIPLEXER4 is

begin

process ( D, S )

begin

-- if文による出力の場合分け

if ( S = "00" ) then

Y <= ( 0 => D, others => '0' );

elsif ( S = "01" ) then

Y <= ( 1 => D, others => '0' );

elsif ( S = "10" ) then

Y <= ( 2 => D, others => '0' );

else

Y <= ( 3 => D, others => '0' );

end if;

end process;

end DATAFLOW;

【Verilog-HDL記述】

module DEMULTIPLEXER4 (

D,

S,

Y

);

input D;

input[ 1 : 0 ] S;

output[ 3 : 0 ] Y;

// 条件演算子による出力の場合分け

assign Y[ 0 ] = ( S == 2'b00 ) ? D : 1'b0;

assign Y[ 1 ] = ( S == 2'b01 ) ? D : 1'b0;

assign Y[ 2 ] = ( S == 2'b10 ) ? D : 1'b0;

assign Y[ 3 ] = ( S == 2'b11 ) ? D : 1'b0;

endmodule