【VHDL記述】

library IEEE;

use IEEE.std_logic_1164.all;

entity SHIFT_REG4 is

port( CK, DIN : in std_logic;

DOUT : out std_logic );

end SHIFT_REG4;

architecture BEHAVIOR of SHIFT_REG4 is

signal TMP : std_logic_vector(3 downto 0);

begin

process begin

wait until CK'event and CK = '0';

TMP <= TMP(2 downto 0) & DIN;

end process;

DOUT <= TMP(3);

end BEHAVIOR;

【Verilog-HDL記述】

module SHIFT_REG4 (

CK, DIN,

DOUT

);

input CK, DIN;

output DOUT;

reg[ 3: 0 ] TMP;

always @ ( negedge CK ) begin

TMP <= { TMP[ 2 : 0 ], DIN };

end

assign DOUT = TMP[3];

endmodule