【VHDL記述】

library IEEE;

use IEEE.std_logic_1164.all;

entity TESTBENCH_DT_1 is

end TESTBENCH_DT_1;

architecture SIM_DATA of TESTBENCH_DT_1 is

component MULTIPLEXER4

port ( D : in std_logic_vector(3 downto 0);

S : in std_logic_vector(1 downto 0);

Y : out std_logic );

end component;

component DEMULTIPLEXER4

port ( D : in std_logic;

S : in std_logic_vector(1 downto 0);

Y : out std_logic_vector(3 downto 0));

end component;

signal S_Y : std_logic;

signal S_S : std_logic_vector(1 downto 0);

signal S_A, S_B : std_logic_vector(3 downto 0);

begin

M1 : MULTIPLEXER4 port map (S_A, S_S, S_Y);

M2 : DEMULTIPLEXER4 port map (S_Y, S_S, S_B);

-- テストベクトル(信号値と時間の指定による記述)

P1 : process

begin

S_S <= "00"; wait for 10 ns;

S_S <= "01"; wait for 10 ns;

S_S <= "10"; wait for 10 ns;

S_S <= "11"; wait for 10 ns;

end process;

P2 : process

begin

S_A <= "0000"; wait for 40 ns;

S_A <= "0010"; wait for 40 ns;

S_A <= "0100"; wait for 40 ns;

S_A <= "0110"; wait for 40 ns;

S_A <= "1000"; wait for 40 ns;

S_A <= "1001"; wait for 40 ns;

end process;

end SIM_DATA;

configuration CFG_DT_1 of TESTBENCH_DT_1 is

for SIM_DATA

end for;

end CFG_DT_1;

【Verilog-HDL記述】

`timescale 1 ns / 10 ps

module TESTBENCH_DT_1;

reg[ 3 : 0 ] S_A;

wire[ 3 : 0 ] S_B;

reg[ 1 : 0 ] S_S;

wire S_Y;

MULTIPLEXER4 M1 (S_A, S_S, S_Y);

DEMULTIPLEXER4 M2 (S_Y, S_S, S_B);

// テストベクトル(信号値と時間の指定による記述)

always begin

S_S = 2'b00;

#10 S_S = 2'b01;

#10 S_S = 2'b10;

#10 S_S = 2'b11;

#10 ;

end

always begin

S_A = 4'b0000;

#40 S_A = 4'b0010;

#40 S_A = 4'b0100;

#40 S_A = 4'b0110;

#40 S_A = 4'b1000;

#40 S_A = 4'b1001;

#40 ;

end

// シミュレーション結果の表示(システム・タスク)

initial $monitor( $stime, " Y=%b S=%b A=%b B=%b", S_Y, S_S, S_A, S_B);

endmodule