データ伝送回路のテストベンチ(プログラム的な記述)
掲載ページ:89、リスト番号:4.17
【VHDL記述】
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
entity TESTBENCH_DT_3 is
end TESTBENCH_DT_3;
architecture SIM_DATA of TESTBENCH_DT_3 is
component MULTIPLEXER4
port ( D : in std_logic_vector(3 downto 0);
S : in std_logic_vector(1 downto 0);
Y : out std_logic );
end component;
component DEMULTIPLEXER4
port ( D : in std_logic;
S : in std_logic_vector(1 downto 0);
Y : out std_logic_vector(3 downto 0));
end component;
signal S_Y : std_logic;
signal S_S : std_logic_vector(1 downto 0);
signal S_A, S_B : std_logic_vector(3 downto 0);
begin
M1 : MULTIPLEXER4 port map (S_A, S_S, S_Y);
M2 : DEMULTIPLEXER4 port map (S_Y, S_S, S_B);
-- テストベクトル(プログラム的な記述)
P1 : process
begin
for I in 0 to 15 loop
S_A <= conv_std_logic_vector(I, 4);
for J in 0 to 3 loop
S_S <= conv_std_logic_vector(J, 2);
wait for 10 ns;
end loop;
end loop;
end process;
end SIM_DATA;
configuration CFG_DT_3 of TESTBENCH_DT_3 is
for SIM_DATA
end for;
end CFG_DT_3;
【Verilog-HDL記述】
`timescale 1 ns / 10 ps
module TESTBENCH_DT_1;
reg[ 3 : 0 ] S_A;
wire[ 3 : 0 ] S_B;
reg[ 1 : 0 ] S_S;
wire S_Y;
integer I, J;
MULTIPLEXER4 M1 (S_A, S_S, S_Y);
DEMULTIPLEXER4 M2 (S_Y, S_S, S_B);
// テストベクトル(プログラム的な記述)
always begin
for ( I = 0; I < 16; I = I + 1 ) begin
S_A = I;
for ( J = 0; J < 4; J = J + 1 ) begin
S_S = J;
#10 ;
end
end
end
// シミュレーション結果の表示(システム・タスク)
initial $monitor( $stime, " Y=%b S=%b A=%b B=%b", S_Y, S_S, S_A, S_B);
endmodule
【シミュレーション結果】